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ICCAD 1992: Santa Clara, California, USA
- Louise Trevillyan, Michael R. Lightner:
1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers. IEEE Computer Society / ACM 1992, ISBN 0-8186-3010-8
DFT to Reduce Test Application Time
- Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer:
Configuring multiple scan chains for minimum test time. 4-8 - Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang:
Overall consideration of scan design and test generation. 9-12 - Yoon-Hwa Choi, Taechul Jung:
Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices. 13-16 - Soo Young Lee, Kewal K. Saluja:
An algorithm to reduce test application time in full scan designs. 17-20
Technology Driven Layout
- Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani:
New channel segmentation model and associated routing algorithm for high performance FPGAs. 22-25 - Kai Zhu, D. F. Wong
:
On channel segmentation design for row-based FPGAs. 26-29 - Akhilesh Tyagi:
VLSI design parsing (preliminary version). 30-34 - Tsung D. Lee, Lawrence P. McNamee:
Aesthetic routing for transistor schematics. 35-38
Lookup Table Based FPGA Synthesis Techniques
- Robert J. Francis:
A tutorial on logic synthesis for lookup-table based FPGAs. 40-47 - Jason Cong, Yuzheng Ding:
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. 48-53 - Yuji Kukimoto, Masahiro Fujita:
Rectification method for lookup-table type FPGA's. 54-61
Advances in Asymptotic Waveform Evaluation
- Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage:
AWE macromodels of VLSI interconnect for circuit simulation. 64-70 - J. Eric Bracken, Vivek Raghavan, Ronald A. Rohrer:
Extension of the asymptotic waveform evaluation technique with the method of characteristics. 71-75 - M. Murat Alaybeyi, John Y. Lee, Ronald A. Rohrer:
Numerical integration algorithms and asymptotic waveform evaluation (AWE). 76-79
Topics in Simulation
- Ashish S. Gadagkar, James R. Armstrong:
Timing distribution in VHDL behavioral models. 82-89 - Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick:
McPOWER: a Monte Carlo approach to power estimation. 90-97 - Daniel Brand:
Exhaustive simulation need not require an exponential number of tests. 98-101
Asynchronous Circuit Synthesis Using STG's
- Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
A unified signal transition graph model for asynchronous control circuit synthesis. 104-111 - Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man:
A generalized state assignment theory for transformation on signal transition graphs. 112-117 - Kuan-Jen Lin, Chen-Shang Lin:
On the verification of state-coding in STGs. 118-122
Clocking of Circuits with Level Sensitive Latches
- Thomas G. Szymanski, Narendra V. Shenoy:
Verifying clock schedules. 124-131 - Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Graph algorithms for clock schedule optimization. 132-136 - Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge:
Identification of critical paths in circuits with level-sensitive latches. 137-141 - Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah:
Using constraint geometry to determine maximum rate pipeline clocking. 142-148
High Density Module Assembly
- Jin-Fuw Lee, Donald T. Tang:
HIMALAYAS - a hierarchical compaction system with a minimized constraint set. 150-157 - Ravi Varadarajan, Cyrus Bamji:
Cloning techniques for hierarchical compaction. 158-161 - Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki:
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. 162-165 - Goro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa:
MOSAIC: a tile-based datapath layout generator. 166-170
Formal Hardware Verification
- Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Automatic compositional minimization in CTL model checking. 172-178 - Enrico Macii, Bernard Plessier, Fabio Somenzi:
Verification of systems containing counters. 179-182 - Filip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas:
Automatic generation and verification of sufficient correctness properties for synchronous processors. 183-187 - Srinivas Devadas, Kurt Keutzer, Sharad Malik
Verification of asynchronous interface circuits with bounded wire delays. 188-195
Techniques for Power and Timing Estimation in CMOS Circuits
- Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Delay and bus current evaluation in CMOS logic circuits. 198-203 - F. Rouatbi, Baher Haroun, Asim J. Al-Khalili:
Power estimation tool for sub-micron CMOS VLSI circuits. 204-209 - Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation. 210-213
Sequential ATPG
- Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
CRIS: a test cultivation program for sequential VLSI circuits. 216-219 - Balkrishna Ramkumar, Prithviraj Banerjee:
Portable parallel test generation for sequential circuits. 220-223 - Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. 224-228
High-Level Design
- Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin:
An effective methodology for functional pipelining. 230-233 - Hironori Komi, Shoichiro Yamada, Kunio Fukunaga:
A scheduling method by stepwise expansion in high-level synthesis. 234-237 - Catherine H. Gebotys:
Optimal synthesis of multichip architectures. 238-241
Classical Simulation
- Yu-Hsu Chang, Andrew T. Yang:
Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuits. 244-247 - Peter Feldmann, Robert C. Melville, Shahriar Moinian:
Automatic differentiation in circuit simulation and device modeling. 248-253 - Kimon W. Michaels, Andrzej J. Strojwas:
A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. 254-257 - Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage:
ETA: electrical-level timing analysis. 258-262
Testing and Diagnosis Methods
- So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
An optimal probe testing algorithm for the connectivity verification of MCM substrates. 264-267 - Gary S. Greenstein, Janak H. Patel:
E-PROOFS: a CMOS bridging fault simulator. 268-271 - Irith Pomeranz, Sudhakar M. Reddy:
On the generation of small dictionaries for fault location. 272-279 - Uwe Hübner, Heinrich Theodor Vierhaus:
Efficient partitioning and analysis of digital CMOS-circuits. 280-283
DSP Applications in High-Level Synthesis
- Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen:
Efficiency improvements for force-directed scheduling. 286-291 - Albert van der Werf, M. J. H. Peek, Emile H. L. Aarts, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh:
Area optimization of multi-functional processing units. 292-299 - Anantha P. Chandrakasan, Miodrag Potkonjak, Jan M. Rabaey, Robert W. Brodersen:
HYPER-LP: a system for power minimization using architectural transformations. 300-303 - Miodrag Potkonjak, Jan M. Rabaey:
Maximally fast and arbitrarily fast implementation of linear computations. 304-308
Analog CAD
- Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner:
Lazy-expansion symbolic expression approximation in SYNAP. 310-317 - Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. D. Martín, José L. Huertas:
Accuate simplification of large symbolic formulae. 318-321 - Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli:
Behavioral simulation for noise in mixed-mode sampled-data systems. 322-326
Multi-View Design Representations for Interactive Synthesis
- Allen C.-H. Wu, Tedd Hadley, Daniel Gajski:
An efficient multi-view design model for real-time interactive synthesis. 328-331 - Roger P. Ang, Nikil D. Dutt
Equivalent design representations and transformations for interactive scheduling. 332-335 - Robert C. Armstrong, Jonathan Allen:
FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databases. 336-343
Timing in High Level Synthesis
- Leon Stok:
False loops through resource sharing. 345-348 - Andreas Kuehlmann, Reinaldo A. Bergamaschi:
Timing analysis in high-level synthesis. 349-354 - Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul:
Accurate layout area and delay modeling for system level design. 355-361
Techniques for High Performance Simulation
- Emily J. Shriver, Karem A. Sakallah:
Ravel: assigned-delay compiled-code logic simulation. 364-368 - Abdulla Bataineh, Füsun Özgüner, Imre Szauter:
Parallel logic and fault simulation algorithms for shared memory vector machines. 369-372 - Naoaki Suganuma, Yukihiro Murata, Satoru Nakata, Shinichi Nagata, Masahiro Tomita, Kotaro Hirano:
Reconfigurable machine and its application to logic diagnosis. 373-376 - Ausif Mahmood, William I. Baker, Jayantha A. Herath, Anura P. Jayasumana:
A logic simulation engine based on a modified data flow architecture. 377-380
Detailed Routing
- Jiri Soukup:
Maze router without a grid map. 382-385 - Mysore Sriram, Sung-Mo Kang:
Detailed layer assignment for MCM routing. 386-389 - De-Sheng Chen, Majid Sarrafzadeh:
A wire-length minimization algorithm for single-layer layouts. 390-393 - Sujoy Mitra, Sudip Nag, Rob A. Rutenbar
System-level routing of mixed-signal ASICs in WREN. 394-399
Topics in Logic Synthesis
- Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer:
On average power dissipation and random pattern testability of CMOS combinational logic networks. 402-407 - Jerry R. Burch, David E. Long:
Efficient Boolean function matching. 408-411 - Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee:
ProperSYN: a portable parallel algorithm for logic synthesis. 412-416 - Seh-Woong Jeong, Fabio Somenzi:
A new algorithm for the binate covering problem and its application to the minimization of Boolean relations. 417-420
Partitioning and Clustering
- Lars W. Hagen, Andrew B. Kahng:
A new approach to effective circuit clustering. 422-427 - Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A probabilistic multicommodity-flow solution to circuit clustering problems. 428-431 - L. James Hwang, Abbas El Gamal:
Optimal replication for min-cut partitioning. 432-435
Interconnect Analysis
- Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jacob K. White:
Efficient techniques for inductance extraction of complex 3-D geometries. 438-442 - Ali El-Zein, Salim Chowdhury:
An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines. 443-448 - Sanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang:
Time domain analysis of nonuniform frequency dependent high-speed interconnects. 449-453
Panel
- Stephen W. Director, Jonathan Allen, J. Duley:
Engineering education: trends and needs (panel). 456
High-Performance Routing
- Ying-Meng Li, Marwan A. Jabri:
A zero-skew clock routing scheme for VLSI circuits. 458-463 - Wasim Khan, Moazzem Hossain, Naveed A. Sherwani:
Zero skew clock routing in multiple-clock synchronous systems. 464-467 - Dirk Theune, Ralf Thiele, Thomas Lengauer, Anja Feldmann
HERO: hierarchical EMC-constrained routing. 468-472 - Qing Zhu, Wayne Wei-Ming Dai:
Perfect-balance planar clock routing with minimal path-length. 473-476
Hardware/Software Co-Design and System Design
- Jane S. Sun, Robert W. Brodersen:
Design of system interface modules. 478-481 - G. Menez, Michel Auguin, Fernand Boéri, C. Carrière:
A partitioning algorithm for system-level synthesis. 482-487 - Pai H. Chou, Ross B. Ortega, Gaetano Borriello:
Synthesis fo the hardware/software interface in microcontroller-based systems. 488-495 - Heinrich Krämer, Jens Müller:
Assignment of global memory elements for multi-process VHDL specifications. 496-501
Retiming and Sensitization Conditions
- Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
Performance optimization of sequential circuits by eliminating retiming bottlenecks. 504-509 - Pranav Ashar, Sujit Dey, Sharad Malik
Exploiting multi-cycle false paths in the performance optimization of sequential circuits. 510-517 - William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Valid clocking in wavepipelined circuits. 518-525 - Shinji Kimura, Shigemi Kashima, Hiromasa Haneda:
Precise timing verification of logic circuits under combined delay model. 526-529
Design Management Styles
- Elisabeth Kupitz, Jürgen Tacken:
DECOR - tightly integrated Design Control and Observation. 532-537 - Peter Bingley, K. Olav ten Bosch, Pieter van der Wolf:
Incorporating design flow management in a framework based CAD system. 538-545 - Venu Vasudevan, Yves Mathys, Jim Tolar:
DAMOCLES: an observer-based approach to design tracking. 546-551
Delay Testing
- Kwang-Ting Cheng
Test generation for delay faults in non-scan and partial scan sequential circuits. 554-559 - Irith Pomeranz, Sudhakar M. Reddy:
An efficient non-enumerative method to estimate path delay fault coverage. 560-567 - Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy:
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. 568-574
Asynchronous Synthesis
- Kenneth Y. Yun, David L. Dill:
Automatic synthesis of 3D asynchronous state machines. 576-580 - Peter A. Beerel
Automatic gate-level synthesis of speed-independent circuits. 581-586 - Venkatesh Akella, Ganesh Gopalakrishnan:
SHILPA: a high-level synthesis system for self-timed circuits. 587-591
Placement and Floorplan Design
- Konrad Doll, Frank M. Johannes, Georg Sigl:
Accurate net models for placement improvement by network flow methods. 594-597 - Bernd Schürmann, Joachim Altmeyer, Gerhard Zimmermann:
Three-phase chip planning - an improved top-down chip planning strategy. 598-605 - Peichen Pan, C. L. Liu:
Area minimization for general floorplans. 606-609
High-Level View of Testing
- Chung-Hsing Chen, Daniel G. Saab:
Behavioral synthesis for testability. 612-615 - Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha:
Behavioral synthesis for easy testability in data path scheduling. 616-619 - Vivek Chickermane, Jaushin Lee, Janak H. Patel:
A comparative study of design for testability methods using high-level and gate-level descriptions. 620-624
Hazards in Combinatorial Synthesis
- Steven M. Nowick, David L. Dill:
Exact two-level minimization of hazard-free logic with multiple-input changes. 626-630 - David S. Kung:
Hazard-non-increasing gate-level optimization algorithms. 631-634
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