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Steven M. Nowick
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- affiliation: Columbia University, New York City, USA
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2020 – today
- 2024
- [j32]Zhe Su
, Simone Ramini, Demetra Coffen Marcolin, Alessandro Veronesi
An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 409-424 (2024) - 2022
- [c72]Davide Bertozzi, Kshitij Bhardwaj, Steven M. Nowick:
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing. AICAS 2022: 178-181 - 2021
- [j31]Davide Bertozzi, Gabriele Miorandi, Alberto Ghiribaldi, Wayne P. Burleson, Greg Sadowski, Kshitij Bhardwaj, Weiwei Jiang, Steven M. Nowick:
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems. IEEE Micro 41(1): 69-81 (2021)
2010 – 2019
- 2019
- [j30]Kshitij Bhardwaj
A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 350-363 (2019) - [c71]Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs. ISLPED 2019: 1-6 - 2017
- [c70]Weiwei Jiang, Steven M. Nowick:
A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach. ASYNC 2017: 1-9 - [c69]Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi:
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow. ASYNC 2017: 10-17 - [c68]Weiwei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski:
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart. DATE 2017: 732-733 - [c67]Davide Bertozzi, Gabriele Miorandi, Mahdi Tala
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip. NGCAS 2017: 77-80 - [c66]Kshitij Bhardwaj, Weiwei Jiang, Steven M. Nowick:
Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer. NOCS 2017: 6:1-6:8 - 2016
- [c65]Kshitij Bhardwaj, Steven M. Nowick:
Achieving lightweight multicast in asynchronous networks-on-chip using local speculation. DAC 2016: 38:1-38:6 - 2015
- [j29]Steven M. Nowick, Montek Singh:
Asynchronous Design - Part 1: Overview and Recent Advances. IEEE Des. Test 32(3): 5-18 (2015) - [j28]Steven M. Nowick, Montek Singh:
Asynchronous Design - Part 2: Systems and Methodologies. IEEE Des. Test 32(3): 19-28 (2015) - [j27]Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick:
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2009-2022 (2015) - [c64]Gabriele Miorandi, Davide Bertozzi, Steven M. Nowick:
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters. ASYNC 2015: 108-115 - [c63]Weiwei Jiang, Kshitij Bhardwaj, Geoffray Lacourba, Steven M. Nowick:
A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's. DAC 2015: 203:1-203:6 - [c62]John Demme, Bipin Rajendran
Increasing reconfigurability with memristive interconnects. ICCD 2015: 351-358 - 2014
- [j26]Christos Vezyrtzis, Weiwei Jiang, Steven M. Nowick, Yannis P. Tsividis:
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate. IEEE J. Solid State Circuits 49(10): 2292-2304 (2014) - [c61]Georgios Faldamis, Weiwei Jiang, Gennette Gill, Steven M. Nowick:
A low-latency asynchronous interconnection network with early arbitration resolution. ASP-DAC 2014: 329-336 - [c60]Gabriele Miorandi, Alberto Ghiribaldi, Steven M. Nowick, Davide Bertozzi:
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study. VLSI-SoC 2014: 1-6 - 2013
- [c59]Jian Liu, Steven M. Nowick, Mingoo Seok:
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages. ASYNC 2013: 1-7 - [c58]Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick:
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. DATE 2013: 332-337 - [c57]Christos Vezyrtzis, Weiwei Jiang, Steven M. Nowick, Yannis P. Tsividis:
A flexible, clockless digital filter. ESSCIRC 2013: 65-68 - [c56]Yu Chen, Mingoo Seok, Steven M. Nowick:
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control. ISLPED 2013: 267-272 - 2012
- [j25]Melinda Y. Agyekum, Steven M. Nowick:
Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 75-88 (2012) - [c55]Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick:
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications. ICCD 2012: 329-336 - 2011
- [j24]Steven M. Nowick, Montek Singh:
High-Performance Asynchronous Pipelines: An Overview. IEEE Des. Test Comput. 28(5): 8-22 (2011) - [j23]Montek Singh, Steven M. Nowick:
Introduction to Special Issue: Asynchrony in System Design. ACM J. Emerg. Technol. Comput. Syst. 7(4): 14:1-14:2 (2011) - [j22]Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin:
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 494-507 (2011) - [c54]Melinda Y. Agyekum, Steven M. Nowick:
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication. DATE 2011: 1370-1375 - [c53]Gennette Gill, Sumedh S. Attarde, Geoffray Lacourba, Steven M. Nowick:
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes. NOCS 2011: 193-200 - 2010
- [j21]Montek Singh, Steven M. Nowick:
ACM Journal on Emerging Technologies in Computing Systems. ACM Trans. Design Autom. Electr. Syst. 16(1): 11:1 (2010) - [j20]Montek Singh, José A. Tierno, Alexander V. Rylyakov, Sergey V. Rylov
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1043-1056 (2010) - [c52]Melinda Y. Agyekum, Steven M. Nowick:
An error-correcting unordered code and hardware support for robust asynchronous global communication. DATE 2010: 765-770 - [c51]Marco Cannizzaro, Weiwei Jiang, Steven M. Nowick:
Practical completion detection for 2-of-N delay-insensitive codes. ICCD 2010: 151-158 - [c50]Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin:
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. NOCS 2010: 43-50
2000 – 2009
- 2009
- [j19]William F. McLaughlin, Amitava Mitra, Steven M. Nowick:
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 923-928 (2009) - 2008
- [j18]Cheoljoo Jeong, Steven M. Nowick:
Technology Mapping and Cell Merger for Asynchronous Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 659-672 (2008) - [c49]Cheoljoo Jeong, Steven M. Nowick:
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation. ASYNC 2008: 95-104 - [c48]Peggy B. McGee, Melinda Y. Agyekum, Moustafa A. Mohamed, Steven M. Nowick:
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication. ASYNC 2008: 116-127 - 2007
- [j17]Montek Singh, Steven M. Nowick:
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 684-698 (2007) - [j16]Montek Singh, Steven M. Nowick:
The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1256-1269 (2007) - [j15]Montek Singh, Steven M. Nowick:
The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1270-1283 (2007) - [c47]Cheoljoo Jeong, Steven M. Nowick:
Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation. ASP-DAC 2007: 622-627 - [c46]Melinda Y. Agyekum, Steven M. Nowick:
A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. ASYNC 2007: 129-142 - [c45]Amitava Mitra, William F. McLaughlin, Steven M. Nowick:
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. ASYNC 2007: 186-195 - [c44]Peggy B. McGee, Steven M. Nowick:
An efficient algorithm for time separation of events in concurrent systems. ICCAD 2007: 180-187 - 2006
- [c43]Cheoljoo Jeong, Steven M. Nowick:
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. ASYNC 2006: 128-137 - 2005
- [c42]Peggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.:
Efficient performance analysis of asynchronous systems based on periodicity. CODES+ISSS 2005: 225-230 - [c41]Peggy B. McGee, Steven M. Nowick:
A lattice-based framework for the classification and design of asynchronous pipelines. DAC 2005: 491-496 - [c40]Feng Shi, Yiorgos Makris
Test generation for ultra-high-speed asynchronous pipelines. ITC 2005: 10 - 2004
- [j14]Yee William Li, George Patounakis, Kenneth L. Shepard, Steven M. Nowick:
High-throughput asynchronous datapath with software-controlled voltage scaling. IEEE J. Solid State Circuits 39(4): 704-708 (2004) - [j13]Tiberiu Chelcea, Steven M. Nowick:
Robust interfaces for mixed-timing systems. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 857-873 (2004) - [c39]Cheoljoo Jeong, Steven M. Nowick:
Fast hazard detection in combinational circuits. DAC 2004: 592-595 - 2003
- [j12]Soha Hassoun, Steven M. Nowick, Leon Stok:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 662-664 (2003) - [c38]Steven M. Nowick, Charles W. O'Donnell:
On the Existence of Hazard-Free Multi-Level Logic. ASYNC 2003: 109-120 - [c37]Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick:
Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. ASYNC 2003: 216-226 - 2002
- [c36]José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick:
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. ASYNC 2002: 84-95 - [c35]Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. DAC 2002: 405-410 - [c34]Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards:
A Burst-Mode Oriented Back-End for the Balsa Synthesis System. DATE 2002: 330-337 - [c33]Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick:
High-Speed Non-Linear Asynchronous Pipelines. DATE 2002: 1000-1007 - [c32]Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS 2002: 355-360 - 2001
- [b2]Robert M. Fuhrer, Steven M. Nowick:
Sequential optimization of asynchronous and synchronous fintie-state machines. Springer 2001, ISBN 978-0-7923-7425-1, pp. I-XX, 1-258 - [c31]Tiberiu Chelcea, Steven M. Nowick:
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. DAC 2001: 21-26 - [c30]Michael Theobald, Steven M. Nowick:
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. DAC 2001: 263-268 - [c29]Montek Singh, Steven M. Nowick:
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. ICCD 2001: 9-17 - 2000
- [j11]Montek Singh, Steven M. Nowick:
Synthesis for logical initializability of synchronous finite-state machines. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 542-557 (2000) - [c28]Montek Singh, Steven M. Nowick:
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. ASYNC 2000: 198- - [c27]Tiberiu Chelcea, Steven M. Nowick:
Low-Latency Asynchronous FIFO's Using Token Rings. ASYNC 2000: 210-
1990 – 1999
- 1999
- [j10]Steven M. Nowick, Mark B. Josephs
Special Issue On Asynchronous Circuits And Systems. Proc. IEEE 87(2): 219-222 (1999) - [j9]Kees van Berkel, Mark B. Josephs, Steven M. Nowick:
Applications of asynchronous circuits. Proc. IEEE 87(2): 223-233 (1999) - [j8]Mark B. Josephs
Modeling and design of asynchronous circuits. Proc. IEEE 87(2): 234-242 (1999) - [c26]Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. DAC 1999: 104-109 - [c25]Robert M. Fuhrer, Steven M. Nowick:
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic. ICCAD 1999: 7-13 - 1998
- [j7]Michael Theobald, Steven M. Nowick:
Fast heuristic and exact algorithms for two-level hazard-free logic minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1130-1147 (1998) - [j6]Luis A. Plana
Architectural optimization for low-power nonpipelined asynchronous systems. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 56-65 (1998) - [c24]Martin Benes, Steven M. Nowick, Andrew Wolfe:
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. ASYNC 1998: 43- - [c23]Michael Theobald, Steven M. Nowick:
An Implicit Method for Hazard-Free Two-Level Logic Minimization. ASYNC 1998: 58-69 - 1997
- [j5]Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1514-1521 (1997) - [c22]Martin Benes, Andrew Wolfe, Steven M. Nowick:
A High-Speed Asynchronous Decompression Circuit for Embedded Processors. ARVLSI 1997: 219-237 - [c21]Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel:
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ASYNC 1997: 210- - [c20]Robert M. Fuhrer, Steven M. Nowick:
OPTIMIST: state minimization for optimal 2-level logic implementation. ICCAD 1997: 308-315 - [c19]Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design. ICCD 1997: 662-668 - [c18]Steven M. Nowick, Michael Theobald:
Synthesis of low-power asynchronous circuits in a specified environment. ISLPED 1997: 92-95 - [c17]Montek Singh, Steven M. Nowick:
Synthesis for Logical Initializability of Synchronous Finite State Machines. VLSI Design 1997: 76-81 - 1996
- [c16]Michael Theobald, Steven M. Nowick, Tao Wu:
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. DAC 1996: 71-76 - [c15]Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick:
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. DAC 1996: 77-82 - [c14]Luis A. Plana
Concurrency-oriented optimization for low-power asynchronous systems. ISLPED 1996: 151-156 - [c13]Montek Singh, Steven M. Nowick:
Synthesis-for-Initializability of Asynchronous Sequential Machines. ITC 1996: 232-241 - 1995
- [j4]Steven M. Nowick, David L. Dill:
Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 986-997 (1995) - [c12]Robert M. Fuhrer, Bill Lin, Steven M. Nowick:
Algorithms for the optimal state assignment of asynchronous state machines. ARVLSI 1995: 59-75 - [c11]Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh:
Estimation and bounding of energy consumption in burst-mode control circuits. ICCAD 1995: 26-33 - [c10]Robert M. Fuhrer, Bill Lin, Steven M. Nowick:
Symbolic hazard-free minimization and encoding of asynchronous finite state machines. ICCAD 1995: 604-611 - [c9]Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. VLSI Design 1995: 171-176 - 1994
- [j3]Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick:
A correctness criterion for asynchronous circuit validation and optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1309-1318 (1994) - [c8]Steven M. Nowick, Bill Coates:
UCLOCK: Automated Design of High-Peformance Unclocked State Machines. ICCD 1994: 434-441 - 1993
- [b1]Steven M. Nowick:
Automatic synthesis of burst-mode asynchronous controllers. Stanford University, USA, 1993 - [j2]Steven M. Nowick, Mark E. Dean, David L. Dill, Mark Horowitz:
The design of a high-performance cache controller: a case study in asynchronous synthesis. Integr. 15(3): 241-262 (1993) - 1992
- [j1]David L. Dill, Steven M. Nowick, Robert F. Sproull:
Specification and Automatic Verification of Self-Timed Queues. Formal Methods Syst. Des. 1(1): 29-60 (1992) - [c7]Steven M. Nowick, David L. Dill:
Exact two-level minimization of hazard-free logic with multiple-input changes. ICCAD 1992: 626-630 - [c6]Steven M. Nowick, Kenneth Y. Yun, David L. Dill:
Practical Asynchronous Controller Design. ICCD 1992: 341-345 - [c5]Kenneth Y. Yun, David L. Dill, Steven M. Nowick:
Synthesis of 3D Asynchronous State Machines. ICCD 1992: 346-350 - 1991
- [c4]Steven M. Nowick, David L. Dill:
Automatic Synthesis of Locally-Clocked Asynchronous State Machines. ICCAD 1991: 318-321 - [c3]Steven M. Nowick, David L. Dill:
Synthesis of Asynchronous State Machines Using A Local Clock. ICCD 1991: 192-197
1980 – 1989
- 1989
- [c2]Steven M. Nowick, David L. Dill:
Practicality of state-machine verification of speed-independent circuits. ICCAD 1989: 266-269 - [c1]David L. Dill, Steven M. Nowick, Robert F. Sproull:
Automatic verification of speed-independent circuits with Petri net specifications. ICCD 1989: 212-216
Coauthor Index
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