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Masao Sato
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1990 – 1999
- 1997
- [j2]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. J. Circuits Syst. Comput. 7(5): 373-394 (1997) - [c8]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC 1997: 569-578 - 1995
- [c7]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995 - 1994
- [c6]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163 - [c5]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486 - 1992
- [c4]Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki:
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. ICCAD 1992: 162-165 - 1991
- [c3]Wayne Wei-Ming Dai, Raymond Kong, Masao Sato:
Routability of a Rubber-Band Sketch. DAC 1991: 45-48 - 1990
- [c2]Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki:
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. DAC 1990: 646-649
1980 – 1989
- 1987
- [j1]Masao Sato, Tatsuo Ohtsuki:
Applications of computational geometry to VLSI layout pattern design. Integr. 5(3-4): 303-317 (1987) - [c1]Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh:
A Dynamic and Efficient Representation of Building-Block Layout. DAC 1987: 376-384
Coauthor Index
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