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Yuzheng Ding
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2010 – 2019
- 2016
- [r2]Jason Cong, Yuzheng Ding:
FPGA Technology Mapping. Encyclopedia of Algorithms 2016: 773-777
2000 – 2009
- 2008
- [r1]Jason Cong, Yuzheng Ding:
FPGA Technology Mapping. Encyclopedia of Algorithms 2008 - 2005
- [c10]Yuzheng Ding, Peter Suaris, Nan-Chi Chou:
The effect of post-layout pin permutation on timing. FPGA 2005: 41-50 - 2004
- [c9]Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou:
Incremental physical resynthesis for timing optimization. FPGA 2004: 99-108
1990 – 1999
- 1999
- [c8]Jason Cong, Chang Wu, Yuzheng Ding:
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA 1999: 29-35 - 1996
- [j9]Jason Cong, Yuzheng Ding:
Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996) - [c7]Jason Cong, John Peck, Yuzheng Ding:
RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA 1996: 137-143 - 1995
- [c6]Jason Cong, Yuzheng Ding:
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA 1995: 82-88 - 1994
- [j8]Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen:
LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. 18(4): 507-516 (1994) - [j7]Jason Cong, Yuzheng Ding:
On nominal delay minimization in LUT-based FPGA technology mapping. Integr. 18(1): 73-94 (1994) - [j6]Yuzheng Ding, Mark Allen Weiss:
On the Complexity of Building an Interval Heap. Inf. Process. Lett. 50(3): 143-144 (1994) - [j5]Jason Cong, Yuzheng Ding:
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 1-12 (1994) - [j4]Jason Cong, Yuzheng Ding:
On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 137-148 (1994) - 1993
- [j3]Yuzheng Ding, Mark Allen Weiss:
The Relaxed min-max Heap. Acta Informatica 30(3): 215-231 (1993) - [c5]Jason Cong, Yuzheng Ding:
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC 1993: 213-218 - [c4]Jason Cong, Yuzheng Ding:
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD 1993: 110-114 - [c3]Yuzheng Ding, Mark Allen Weiss:
The K-D Heap: An Efficient Multi-dimensional Priority Queue. WADS 1993: 302-313 - 1992
- [j2]Yuzheng Ding, Mark Allen Weiss:
Best case lower bounds for Heapsort. Computing 49(1): 1-9 (1992) - [j1]Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9(3): 7-20 (1992) - [c2]Jason Cong, Yuzheng Ding:
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD 1992: 48-53 - [c1]Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158
Coauthor Index
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