default search action
20. ACM Great Lakes Symposium on VLSI 2010: Providence, Rhode Island, USA
- R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand:
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. ACM 2010, ISBN 978-1-4503-0012-4
Invited speaker 1
- Vincenzo Rana, Donatella Sciuto:
A novel design framework for the design of reconfigurable systems based on NoCs. 1-2
CAD I
- Mohammad Reza Kakoee, Igor Loi, Luca Benini
:
A new physical routing approach for robust bundled signaling on NoC links. 3-8 - Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
Bus via reduction based on floorplan revising. 9-14 - Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware nonuniform clock mesh synthesis. 15-20 - Jin Shi, Yici Cai:
Scaling power/ground solvers on multi-core with memory bandwidth awareness. 21-26 - Bo-Shiun Wu, Tsung-Yi Ho
Bus-pin-aware bus-driven floorplanning. 27-32
VLSI circuits I
- Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi:
8Gb/s capacitive low power and high speed 4-PWAM transceiver design. 33-38 - Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni
A low power, variable resolution two-step flash ADC. 39-44 - HeungJun Jeon, Yong-Bin Kim:
A low-offset high-speed double-tail dual-rail dynamic latched comparator. 45-48 - Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin
Via configurable three-input lookup-tables for structured ASICs. 49-54 - Sreeharsha Tavva, Dhireesha Kudithipudi:
Variation tolerant 9T SRAM cell design. 55-60
Testing I
- Hao Chen, Jie Han:
Stochastic computational models for accurate reliability evaluation of logic circuits. 61-66 - Taniya Siddiqua, Sudhanva Gurumurthi:
A multi-level approach to reduce the impact of NBTI on processor functional units. 67-72 - Jaynarayan T. Tudu
Graph theoretic approach for scan cell reordering to minimize peak shift power. 73-78 - Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Gating internal nodes to reduce power during scan shift. 79-84 - Aashish Pant, Puneet Gupta
Software adaptation in quality sensitive applications to deal with hardware variability. 85-90
Poster session I
- Liang Shi, Chun Jason Xue
Write activity reduction on flash main memory via smart victim cache. 91-94 - Andrea Calimera
Aging effects of leakage optimizations for caches. 95-98 - David Cuesta, José Luis Ayala, José Ignacio Hidalgo
Thermal-aware floorplanning exploration for 3D multi-core architectures. 99-102 - Rance Rodrigues, Sandip Kundu:
A mask double patterning technique using litho simulation by wavelet transform. 103-106 - Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden:
An effective approach for large scale floorplanning. 107-110 - Keisuke Inoue, Mineo Kaneko:
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. 111-114 - Tao Lin, Sheqin Dong, Bei Yu, Song Chen
A revisit to voltage partitioning problem. 115-118 - Jin-Tai Yan, Zhi-Wei Chen:
Resource-constrained timing-driven link insertion for critical delay reduction. 119-122 - Kanupriya Gulati, Sunil P. Khatri:
Boolean satisfiability on a graphics processor. 123-126 - Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard:
Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. 127-130 - Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Improving the testability and reliability of sequential circuits with invariant logic. 131-134 - Bo Yao, Irith Pomeranz, Sudhakar M. Reddy:
Deterministic broadside test generation for transition path delay faults. 135-138 - Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
A delay measurement method using a shrinking clock signal. 139-142 - Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Energy-efficient redundant execution for chip multiprocessors. 143-146 - Kanak Agarwal:
On-die sensors for measuring process and environmental variations in integrated circuits. 147-150 - Xin He, Afshin Abdollahi:
Cost aware fault tolerant logic synthesis in presence of soft errors. 151-154 - Sumanta Chaudhuri
Design of embedded MRAM macros for memory-in-logic applications. 155-158 - Vikas Kaushal, Ignacio Iñiguez-de-la-Torre
Topology impact on the room temperature performance of THz-range ballistic deflection transistors. 159-162 - Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi:
Performance assessment of analog circuits with carbon nanotube FET (CNFET). 163-166 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Read-out schemes for a CNTFET-based crossbar memory. 167-170
Invited speaker 2
- Ron Weiss:
Synthetic biology: from modules to systems. 171-172
CAD II
- Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram:
Dominant critical gate identification for power and yield optimization in logic circuits. 173-178 - Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. 179-184 - Stergios Stergiou, Jawahar Jain:
Dynamically resizable binary decision diagrams. 185-190 - Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez:
Fast instruction cache modeling for approximate timed HW/SW co-simulation. 191-196 - Shinya Abe, Kenichi Shinkai, Masanori Hashimoto
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. 197-202
Low power I
- Francesco Zanini, David Atienza, Giovanni De Micheli, Stephen P. Boyd:
Online convex optimization-based algorithm for thermal management of MPSoCs. 203-208 - John Sartori, Rakesh Kumar:
Overscaling-friendly timing speculation architectures. 209-214 - Omer Khan, Sandip Kundu:
A model to exploit power-performance efficiency in superscalar processors via structure resizing. 215-220 - Mohamed M. Sabry, José L. Ayala, David Atienza:
Thermal-aware compilation for system-on-chip processing architectures. 221-226 - Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
A linear statistical analysis for full-chip leakage power with spatial correlation. 227-232
VLSI design and post-CMOS technology
- Xuebei Yang, Gianluca Fiori
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. 233-238 - Marisha Rawlins, Ann Gordon-Ross:
Lightweight runtime control flow analysis for adaptive loop caching. 239-244 - Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra:
Low power nanoscale buffer management for network on chip routers. 245-250 - Shruti Vyas, Aswin Sreedhar, Sandip Kundu:
TURBONFS: turbo nand flash search. 251-256 - Soontae Kim, Jongmin Lee:
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. 257-262
Emerging technology
- Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram:
Graphene tunneling FET and its applications in low-power circuit design. 263-268 - Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas:
Scalable identification of threshold logic functions. 269-274 - Xiaojun Ma, Masoud Hashempour, Lei Wang, Fabrizio Lombardi:
Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates. 275-280 - Pooya Jannaty, Florian C. Sabou, R. Iris Bahar
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. 281-286 - Harika Manem, Garrett S. Rose
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. 287-292
Special session I: system-level SoC design
- Andrea Acquaviva, Andrea Calimera
An integrated thermal estimation framework for industrial embedded platforms. 293-298 - Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban:
Power-efficient, reliable microprocessor architectures: modeling and design methods. 299-304 - Mohamed M. Sabry, Martino Ruggiero, Pablo García Del Valle:
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs. 305-310 - Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries:
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. 311-316 - Pinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi:
Challenges and methodologies for efficient power budgeting across the die. 317-322
VLSI design
- Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. 323-328 - Renatas Jakushokas, Eby G. Friedman:
Line width optimization for interdigitated power/ground networks. 329-334 - Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier:
Thermal-aware voltage droop compensation for multi-core architectures. 335-340 - Basab Datta, Wayne P. Burleson:
Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. 341-346 - Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu:
Collaborative voltage scaling with online STA and variable-latency datapath. 347-352
Poster session II
- Feng Liu, QingPing Tan, Xiaoyu Song, Naeem Abbasi:
AOP-based high-level power estimation in SystemC. 353-356 - Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu:
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes. 357-360 - Anja Niedermeier, Kjetil Svarstad
The challenges of implementing fine-grained power gating. 361-364 - Raid Ayoub, Alex Orailoglu:
Performance and energy efficient cache migrationapproach for thermal management in embedded systems. 365-368 - Sumanth Amarchinta, Dhireesha Kudithipudi:
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. 369-372 - Anuj Pushkarna, Hamid Mahmoodi
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. 373-376 - Selçuk Köse
On-chip point-of-load voltage regulator for distributed power supplies. 377-380 - Pey-Chang Kent Lin, Sunil P. Khatri:
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. 381-384 - Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski:
Out-of-order issue logic using sorting networks. 385-388 - Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors:
On-chip power supply noise and its implications on timing. 389-392 - Kagan Irez
Characteristics of MS-CMOS logic in sub-32nm technologies. 393-396 - Omer Khan, Sandip Kundu:
A self-adaptive scheduler for asymmetric multi-cores. 397-400 - Ilya Chukhman, Peter Petrov:
Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. 401-404 - Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Design of self correcting radiation hardened digital circuits using decoupled ground bus. 405-408 - Hai Lin, Yunsi Fei
A novel multi-objective instruction synthesis flow for application-specific instruction set processors. 409-412 - Ankit More, Baris Taskin:
Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. 413-416
CAD III
- Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen:
Ordered escape routing via routability-driven pin assignment. 417-422 - De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang:
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. 423-428 - Zheng Liu, Lihong Zhang:
Performance-constrained template-driven retargeting for analog and RF layouts. 429-434 - Wentao Sui, Sheqin Dong, Jinian Bian:
Wirelength-driven force-directed 3D FPGA placement. 435-440 - Pranab Roy, Hafizur Rahaman
A novel droplet routing algorithm for digital microfluidic biochips. 441-446
VLSI circuits II
- Emre Salman, Eby G. Friedman:
Methodology to achieve higher tolerance to delay variations in synchronous circuits. 447-452 - Basab Datta, Wayne P. Burleson:
Circuit-level NBTI macro-models for collaborative reliability monitoring. 453-458 - Jun Wu, Yong-Bin Kim, Minsu Choi:
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. 459-464 - Jean Christoph Jung
Enhancing debugging of multiple missing control errors in reversible logic. 465-470 - Nariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis
Algorithm and hardware complexity reduction techniques for k-best sphere decoders. 471-476
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-15 01:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: