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2020 – today
- 2024
- [c99]Xu Wang, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors:
Unfolded SiBM BCH Decoders for High- Throughput Low-Latency Applications. ISVLSI 2024: 216-221 - [c98]Erik Börjeson, Ekaterina Deriushkina, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors:
Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers. OFC 2024: 1-3 - [c97]Erik Börjeson, Keren Liu, Christian Häger, Per Larsson-Edefors:
Real-Time Implementation of Machine-Learning DSP. OFC 2024: 1-3 - [c96]Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson:
Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype. OFC 2024: 1-3 - 2023
- [c95]Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors:
FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training. OFC 2023: 1-3 - [c94]Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson:
Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524 km of Live Aerial Fiber. OFC 2023: 1-3 - 2022
- [c93]Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson, Per Larsson-Edefors:
Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs. NorCAS 2022: 1-6 - [c92]Per Larsson-Edefors, Erik Börjeson:
Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP. OFC 2022: 1-3 - [c91]Mikael Mazur, Jorge C. Castellanos, Roland Ryf, Erik Börjeson, Tracy Chodkiewicz, Valey Kamalov, Shuang Yin, Nicolas K. Fontaine, Haoshuo Chen, Lauren Dallachiesa, Steve Corteselli, Philip Copping, Jürgen Gripp, Aurelien Mortelette, Benoit Kowalski, Rodney Dellinger, David T. Neilson, Per Larsson-Edefors:
Transoceanic Phase and Polarization Fiber Sensing using Real-Time Coherent Transceiver. OFC 2022: 1-3 - [c90]Mikael Mazur, Lauren Dallachiesa, Nicolas K. Fontaine, Roland Ryf, Erik Börjeson, Haoshuo Chen, Hirotaka Sakuma, Takafumi Ohtsuka, Tetsuya Hayashi, Takemi Hasegawa, Hidehisa Tazawa, David T. Neilson, Per Larsson-Edefors:
Real-Time Transmission over 2×55 km All 7-Core Coupled-Core Multi-Core Fiber Link. OFC 2022: 1-3 - [c89]Mikael Mazur, Roland Ryf, Nicolas K. Fontaine, Andrea Marotta, Erik Börjeson, Lauren Dallachiesa, Haoshuo Chen, Tetsuya Hayashi, Takuji Nagashima, Tetsuya Nakanishi, Tetsu Morishima, Fabio Graziosi, Luca Palmieri, David T. Neilson, Per Larsson-Edefors, Antonio Mecozzi, Cristian Antonelli:
Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers. OFC 2022: 1-3 - [i3]Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors:
FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training. CoRR abs/2212.03515 (2022) - 2021
- [j10]Vikram Jain
, Christoffer Fougstedt
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 25-34 (2021) - [c88]Erik Börjeson, Per Larsson-Edefors:
Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems. OFC 2021: 1-3 - 2020
- [c87]Erik Börjeson, Per Larsson-Edefors:
Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations. OFC 2020: 1-3 - [c86]Christoffer Fougstedt, Oscar Gustafsson, Cheolyong Bae, Erik Börjeson, Per Larsson-Edefors:
ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers. OFC 2020: 1-3
2010 – 2019
- 2019
- [c85]Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors:
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication. ICECS 2019: 45-48 - [c84]Erik Börjeson, Christoffer Fougstedt, Per Larsson-Edefors:
ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems. OFC 2019: 1-3 - [c83]Christoffer Fougstedt, Alireza Sheikh, Alexandre Graell i Amat, Gianluigi Liva, Per Larsson-Edefors:
Energy-Efficient Soft-Assisted Product Decoders. OFC 2019: 1-3 - [c82]Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors:
Hardware Considerations for Selection Networks. VLSI-SoC 2019: 40-45 - 2018
- [c81]Christoffer Fougstedt, Christian Häger
ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters. ECOC 2018: 1-3 - [c80]Lars Lundberg, Erik Börjeson, Christoffer Fougstedt, Mikael Mazur, Magnus Karlsson, Peter A. Andrekson, Per Larsson-Edefors:
Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels. ECOC 2018: 1-3 - [c79]Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson:
A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI. ESSCIRC 2018: 102-105 - [c78]Christoffer Fougstedt, Per Larsson-Edefors:
Energy-Efficient High-Throughput Staircase Decoders. OFC 2018: 1-3 - [c77]Erik Ryman, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors:
Custom versus Cell-Based ASIC Design for Many-Channel Correlators. SiPS 2018: 176-180 - [i2]Christoffer Fougstedt, Christian Häger, Lars J. Svensson, Henry D. Pfister, Per Larsson-Edefors:
ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters. CoRR abs/1806.07223 (2018) - [i1]Christoffer Fougstedt, Alireza Sheikh, Alexandre Graell i Amat, Gianluigi Liva, Per Larsson-Edefors:
Energy-Efficient Soft-Assisted Product Decoders. CoRR abs/1810.12054 (2018) - 2017
- [c76]Gabriel Ortiz, Lars J. Svensson, Erik Alveflo, Per Larsson-Edefors:
Instruction level energy model for the Adapteva Epiphany multi-core processor. Conf. Computing Frontiers 2017: 380-384 - [c75]Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson:
Improved Low-Power LDPC FEC for Coherent Optical Systems. ECOC 2017: 1-3 - [c74]Christoffer Fougstedt, Lars J. Svensson, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors:
Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization. ECOC 2017: 1-3 - [c73]Erik Ryman, Anders Emrich, Lars J. Svensson, Per Larsson-Edefors:
A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry. ESSCIRC 2017: 39-42 - [c72]Christoffer Fougstedt, Mikael Mazur, Lars J. Svensson, Henrik Eliasson, Magnus Karlsson, Per Larsson-Edefors:
Time-domain digital back propagation: Algorithm and finite-precision implementation aspects. OFC 2017: 1-3 - [c71]Gabriel Ortiz, Fredrik Treven, Lars J. Svensson, Per Larsson-Edefors, Sebastian Johansson-Mauricio:
A framework for a relative real-time tracking system based on ultra-wideband technology. WPNC 2017: 1-6 - 2016
- [c70]Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander
Redesigning a tagless access buffer to require minimal ISA changes. CASES 2016: 19:1-19:10 - [c69]Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Practical way halting by speculatively accessing halt tags. DATE 2016: 1375-1380 - [c68]Alen Bardizbanyan, Oskar Andersson
Logic filter cache for wide-VDD-range processors. ICECS 2016: 376-379 - [c67]Christoffer Fougstedt, Pontus Johannisson, Lars J. Svensson, Per Larsson-Edefors:
Dynamic equalizer power dissipation optimization. OFC 2016: 1-3 - 2015
- [c66]Kevin Cushon
Energy-efficient soft-decision LDPC FEC For long-haul optical communication. ECOC 2015: 1-3 - [c65]Krzysztof Szczerba
Impact of forward error correction on energy consumption of VCSEL-based transmitters. ECOC 2015: 1-3 - [c64]Alen Bardizbanyan, Per Larsson-Edefors:
Exploring early and late ALUs for single-issue in-order pipelines. ICCD 2015: 543-548 - [c63]Alen Bardizbanyan, Magnus Själander
Improving Data Access Efficiency by Using Context-Aware Loads and Stores. LCTES 2015: 3:1-3:10 - 2014
- [j9]Erik Ryman, Anders Emrich, Stefan Back Andersson, Lars J. Svensson, Per Larsson-Edefors:
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis. IEEE J. Solid State Circuits 49(11): 2720-2729 (2014) - [c62]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). DATE 2014: 1-4 - [c61]Per Larsson-Edefors, Kjell O. Jeppson:
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration. EWME 2014: 151-154 - [c60]Fredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors:
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications. FPT 2014: 296-299 - 2013
- [j8]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans. Archit. Code Optim. 10(4): 54:1-54:25 (2013) - [c59]Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander
Improving data access efficiency by using a tagless access buffer (TAB). CGO 2013: 28:1-28:11 - [c58]Alen Bardizbanyan, Magnus Själander
Speculative tag access for reduced energy dissipation in set-associative L1 data caches. ICCD 2013: 302-308 - [c57]Erik Ryman, Stefan Back Andersson, J. Riesbeck, S. Dejanovic, Anders Emrich, Per Larsson-Edefors:
A SiGe 8-channel comparator for application in a synthetic aperture radiometer. ISCAS 2013: 845-848 - [c56]Kasyab P. Subramaniyan, Per Larsson-Edefors:
Manufacturable nanometer designs using standard cells with regular layout. ISQED 2013: 398-405 - [c55]Kjell O. Jeppson, Per Larsson-Edefors:
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment. MSE 2013: 48-51 - [c54]Magnus Själander
FlexCore: Implementing an exposed datapath processor. ICSAMOS 2013: 306-313 - 2012
- [c53]Muhammad Waqar Azhar
Viterbi Accelerator for Embedded Processor Datapaths. ASAP 2012: 133-140 - [c52]Fredrik Toft, Niclas Rousk, Jonas Mårtensson
Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers. ISCAS 2012: 3234-3237 - [c51]Tung Thanh Hoang, Per Larsson-Edefors:
Data-Width-Driven Power Gating of Integer Arithmetic Circuits. ISVLSI 2012: 237-242 - [c50]Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander
Configurable RTL model for level-1 caches. NORCHIP 2012: 1-4 - 2011
- [c49]Erik Ryman, Anders Emrich, Stefan Back Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors:
3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry. CICC 2011: 1-4 - [c48]Alen Bardizbanyan, Magnus Själander
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. IPDPS Workshops 2011: 322-325 - [c47]Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors:
Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. ISVLSI 2011: 301-306 - 2010
- [j7]Tung Thanh Hoang, Magnus Själander
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3073-3081 (2010) - [c46]Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP 2010: 55-62 - [c45]Muhammad Waqar Azhar
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD 2010: 675-680 - [c44]Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors:
On-chip power supply noise and its implications on timing. ACM Great Lakes Symposium on VLSI 2010: 389-392 - [c43]Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors:
Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. ISVLSI 2010: 454-455
2000 – 2009
- 2009
- [j6]Magnus Själander
Multiplication Acceleration Through Twin Precision. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1233-1246 (2009) - [j5]Martin Thuresson, Magnus Själander
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. J. Signal Process. Syst. 57(1): 5-19 (2009) - [c42]Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. ICECS 2009: 77-80 - [c41]Kasyab P. Subramaniyan, Emil Axelsson, Per Larsson-Edefors, Mary Sheeran:
Layout exploration of geometrically accurate arithmetic circuits. ICECS 2009: 795-798 - [c40]Tung Thanh Hoang, Magnus Själander
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS 2009: 1-7 - [c39]Thomas Schilling, Magnus Själander
Scheduling for an Embedded Architecture with a Flexible Datapath. ISVLSI 2009: 151-156 - [c38]Tung Thanh Hoang, Magnus Själander
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC 2009: 119-122 - 2008
- [j4]Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Time-domain interconnect characterisation flow for appropriate model segmentation. IET Comput. Digit. Tech. 2(4): 265-274 (2008) - [c37]Magnus Själander
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. ICECS 2008: 33-36 - [c36]Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson:
Noise Interaction Between Power Distribution Grids and Substrate. ISQED 2008: 84-89 - [c35]Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. ISQED 2008: 663-669 - 2007
- [c34]Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis:
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256 - [c33]Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191 - [c32]Magnus Själander
A Flexible Datapath Interconnect for Embedded Applications. ISVLSI 2007: 15-20 - [c31]Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson:
Overdrive Power-Gating Techniques for Total Power Minimization. ISVLSI 2007: 125-132 - [c30]Martin Thuresson, Magnus Själander
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS 2007: 18-25 - 2006
- [j3]Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert:
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 370-379 (2006) - [c29]Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander
Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS 2006 - [c28]Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson:
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563 - 2005
- [c27]Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Accounting for the skin effect during repeater insertion. ACM Great Lakes Symposium on VLSI 2005: 32-37 - [c26]Magnus Själander
A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657 - 2004
- [c25]Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson:
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC 2004: 171-174 - [c24]Magnus Själander
An Efficient Twin-Precision Multiplier. ICCD 2004: 30-33 - [c23]Henrik Eriksson, Per Larsson-Edefors:
Glitch-conscious low-power design of arithmetic circuits. ISCAS (2) 2004: 281-284 - [c22]Henrik Eriksson, Per Larsson-Edefors:
Dynamic pass-transistor dot operators for efficient parallel-prefix adders. ISCAS (2) 2004: 461-464 - [c21]Mindaugas Drazdziulis, Per Larsson-Edefors:
Evaluation of power cut-off techniques in the presence of gate leakage. ISCAS (2) 2004: 745-748 - [c20]Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
On Skin Effect in On-Chip Interconnects. PATMOS 2004: 463-470 - [c19]Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson:
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878 - [c18]Dainius Ciuplys, Per Larsson-Edefors:
On Maximum Current Estimation in CMOS Digital Circuits. VLSI Design 2004: 658-661 - 2003
- [c17]Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors:
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. Applied Informatics 2003: 767-772 - [c16]Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson:
Full-custom vs. standard-cell design flow: an adder case study. ASP-DAC 2003: 507-510 - [c15]Daniel Eckerbert, Per Larsson-Edefors:
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. ASP-DAC 2003: 716-719 - [c14]Mindaugas Drazdziulis, Per Larsson-Edefors:
A gate leakage reduction strategy for future CMOS circuits. ESSCIRC 2003: 317-320 - [c13]Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors:
A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263 - [c12]Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson:
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230 - 2001
- [c11]Daniel Eckerbert, Per Larsson-Edefors:
Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421 - [c10]Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu:
VLSI implementation of CRC-32 for 10 Gigabit Ethernet. ICECS 2001: 1215-1218 - [c9]Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour:
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. ISCAS (4) 2001: 84-87 - [c8]Henrik Eriksson, Per Larsson-Edefors, William P. Marnane
A regular parallel multiplier which utilizes multiple carry-propagate adders. ISCAS (4) 2001: 166-169 - [c7]Daniel Eckerbert, Per Larsson-Edefors:
Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510 - 2000
- [c6]Atila Alvandpour, Per Larsson-Edefors, Christer Svensson:
GLMC: interconnect length estimation by growth-limited multifold clustering. ISCAS 2000: 465-468 - [c5]Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman:
An interconnect-driven design of a DFT processor. ISCAS 2000: 569-572 - [c4]Henrik Eriksson, Per Larsson-Edefors:
Impact of Voltage Scaling on Glitch Power Consumption. PATMOS 2000: 139-148
1990 – 1999
- 1999
- [c3]Atila Alvandpour, Per Larsson-Edefors, Christer Svensson:
A leakage-tolerant multi-phase keeper for wide domino circuits. ICECS 1999: 209-212 - 1998
- [c2]Per Larsson-Edefors:
A Miniature Serial-Data SIMD Architecture. EUROMICRO 1998: 10341-10344 - [c1]Atila Alvandpour, Per Larsson-Edefors, Christer Svensson:
Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. ISLPED 1998: 245-249 - 1996
- [j2]Per Larsson-Edefors:
A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier. IEEE J. Solid State Circuits 31(2): 230-239 (1996) - [j1]Per Larsson-Edefors:
Technology mapping onto very-high-speed standard CMOS hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1137-1144 (1996)
Coauthor Index
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