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Tsang-Chi Kan
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2010 – 2019
- 2015
- [j3]Tsang-Chi Kan, Shanq-Jang Ruan, Ting-Feng Chang, Shih-Hsien Yang:
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration. Circuits Syst. Signal Process. 34(10): 3353-3372 (2015) - 2014
- [j2]Tsang-Chi Kan, Ying-Jung Chen, Hung-Ming Hong, Shanq-Jang Ruan:
Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2): 597-605 (2014) - 2013
- [j1]Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan:
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 142-147 (2013) - [c5]Chih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan:
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning. ISQED 2013: 316-321 - [c4]Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, Shanq-Jang Ruan:
Configurable redundant via-aware standard cell design considering multi-via mechanism. ISQED 2013: 322-326 - 2011
- [c3]Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan:
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate. ACM Great Lakes Symposium on VLSI 2011: 319-324 - [c2]Ting-Feng Chang, Tsang-Chi Kan, Shih-Hsien Yang, Shanq-Jang Ruan:
Enhanced Redundant via Insertion with Multi-via Mechanisms. ISVLSI 2011: 218-223 - 2010
- [c1]Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu:
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes. ACM Great Lakes Symposium on VLSI 2010: 357-360
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