5 nm process

Semiconductor device fabrication
MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977  1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2025
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e

In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 5 nanometer (5 nm) node as the technology node following the 7 nm node.

Single transistor 7 nm scale devices were first produced by researchers in the early 2000s, and in 2003 NEC produced a 5 nm transistor.^[1]

On June 5 2017, IBM revealed that they had created 5 nm silicon chips,^[2] using silicon nanosheets, a break from the usual finFET technology.^[3]

The 5 nm node was once assumed by some experts to be the end of Moore's law.^[4] Transistors smaller than 7 nm will experience quantum tunnelling through their logic gates.^[5] Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the 2 years estimated by Moore's law.^[4]

Beyond 7 nm, major technological advances would have to be made; possible candidates include vortex laser,^[6] MOSFET-BJT dual-mode transistor,^[7] 3D packaging,^[8] microfluidic cooling,^[9] PCMOS,^[10] vacuum transistors,^[11] t-rays,^[12] extreme ultraviolet lithography,^[13] carbon nanotube transistors,^[14] silicon photonics,^[15] graphene,^[16] phosphorene,^[17] organic semiconductors,^[18] gallium arsenide,^[19] indium gallium arsenide,^[20] nano-patterning,^[21] and reconfigurable chaos-based microchips.^[22]

In 2002, IBM produced a 6 nm transistor.^[23]

In 2003, NEC produced a 5 nm transistor.^[1]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center codeveloped a 3 nm transistor, the world's smallest nanoelectronic device based on conventional technology, called a fin field-effect transistor (FinFET).^[24][25] It was the smallest transistor ever produced.

In 2008, transistors one atom thick and ten atoms wide were made by UK researchers. They were carved from graphene, a potential alternative to silicon as the basis of future computing. Graphene is a material made from flat sheets of carbon in a honeycomb arrangement, and is a leading contender. A team at the University of Manchester, UK, used it to make some of the smallest transistors at this time: devices only 1 nm across that contain just a few carbon rings.^[26]

In 2010, an Australian team announced that they fabricated a single functional transistor out of 7 atoms that measured 4 nm in length.^[27][28][29]

In 2012, a team of scientists at Chungbuk National University in South Korea created 2 nm transistor.^[30]

In 2012, a single-atom transistor was fabricated using a phosphorus atom bound to a silicon surface (between two significantly larger electrodes).^[31] This transistor could be said to be a 360 picometer transistor, twice the van der Waals radius of a phosphorus atom; though its covalent radius bound to silicon is likely smaller.^[32] Making transistors smaller than this will require either using elements with smaller atomic radii, or using subatomic particles—like electrons or protons—as functional transistors.

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.^[33][34]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5-nm node.^[35]

In 2016, researchers at Berkeley Lab created a transistor with a working 1-nanometer gate.^[36][37] The field-effect transistor utilized MoS₂ as the channel material, while a carbon nanotube was used to invert the channel. The effective channel length is approximately 1 nm. However, the drain to source pitch was much bigger, with micrometer size.

Although Intel has not yet divulged any certain plans to manufacturers or retailers, their 2009 roadmap projected an end-user release by approximately 2020.^[38][39]
In early 2017 Samsung announced risk production of a 4 nm Node by 2020 as part of its revised roadmap. ^[40]

Lower numbers are better. Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). ^[41][42]