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Hsin-Shu Chen
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2020 – today
- 2024
- [j12]Shih-Bo Yu
, Chun-Hao Liang
Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations. IEEE Trans. Instrum. Meas. 73: 1-12 (2024) - 2023
- [c18]Jun-Yi Wu, Hsin-Shu Chen:
A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback. MWSCAS 2023: 375-379 - 2022
- [c17]Chi-Wei Chen, Chien-Yu Su, Hsin-Shu Chen:
A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC. ISCAS 2022: 3483-3487 - 2021
- [c16]Tun-Yen Liao, Hsin-Shu Chen, Wen-Jong Wu:
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques. ISCAS 2021: 1-4 - 2020
- [c15]Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, Shih-Wei Wu:
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j11]Yao-Sheng Hu
A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. IEEE J. Solid State Circuits 54(10): 2680-2690 (2019) - [c14]Chi-Wei Chen, Hsin-Shu Chen, Wen-Jong Wu:
A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique. MWSCAS 2019: 806-809 - 2018
- [c13]Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen:
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. A-SSCC 2018: 103-106 - [c12]Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, Hsin-Shu Chen:
An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. A-SSCC 2018: 253-256 - [c11]Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. ISCAS 2018: 1-4 - 2017
- [c10]Hsin-Shu Chen, Jia-Nan Tai, Yi-Jan Emery Chen, Jau-Horng Chen:
A current average control method for transient-glitch reduction in variable frequency DC-DC converters. ISCAS 2017: 1-4 - 2016
- [j10]Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 683-692 (2016) - [j9]Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, Hsin-Shu Chen
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1166-1170 (2016) - [c9]Yao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen:
A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC. A-SSCC 2016: 81-84 - [c8]Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen:
A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique. A-SSCC 2016: 149-152 - [c7]Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, Hsin-Shu Chen:
An 8-bit 900MS/S two-step SAR ADC. ISCAS 2016: 2898 - 2014
- [j8]Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 339-343 (2014) - [j7]Chien-Jian Tseng, Chieh-Fan Lai, Hsin-Shu Chen
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2805-2815 (2014) - [c6]Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. A-SSCC 2014: 81-84 - [c5]Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. ISSCC 2014: 196-197 - 2013
- [j6]Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, Hsin-Shu Chen
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2902-2910 (2013) - 2012
- [j5]Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. IEEE J. Solid State Circuits 47(6): 1334-1343 (2012) - [j4]Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen
A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 575-583 (2012) - [c4]Jia-Nan Tai, Hsin-Shu Chen
A highly integrated class-D amplifier using driver delay hysteresis control. VLSI-DAT 2012: 1-4 - [c3]Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. VLSIC 2012: 92-93 - 2010
- [j3]Hsin-Shu Chen
A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop. IEICE Trans. Electron. 93-C(6): 855-860 (2010)
2000 – 2009
- 2009
- [j2]Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, Hsin-Shu Chen
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS. IEEE J. Solid State Circuits 44(11): 3051-3059 (2009) - 2006
- [c2]Sen-Wen Hsiao, Yen-Chih Huang, David Liang, Hung-Wei Kevin Chen, Hsin-Shu Chen:
A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming. ISCAS 2006 - 2001
- [b1]Hsin-Shu Chen:
High-Resolution Nyquist -Rate Analog -to -Digital Converter. University of Illinois Urbana-Champaign, USA, 2001 - [j1]Hsin-Shu Chen
A 14-b 20-Msamples/s CMOS pipelined ADC. IEEE J. Solid State Circuits 36(6): 997-1001 (2001)
1990 – 1999
- 1999
- [c1]Hsin-Shu Chen, A. Ito:
Characterization of 1/f noise vs. number of gate stripes in MOS transistors. ISCAS (2) 1999: 310-313
Coauthor Index
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