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Surajit Kumar Roy
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2020 – today
- 2024
- [j11]Dilip Kumar Maity
, Surajit Kumar Roy, Chandan Giri:
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs. Integr. 94: 102088 (2024) - 2023
- [j10]Sourav Ghosh
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation. J. Electron. Test. 39(1): 89-102 (2023) - [j9]Tapobrata Dhar
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection. J. Electron. Test. 39(4): 447-463 (2023) - [c25]Sourav Ghosh, Surajit Kumar Roy, Chandan Giri:
Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip. iSES 2023: 81-86 - 2022
- [j8]Dilip Kumar Maity
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18(4): 70:1-70:23 (2022) - [j7]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. Microelectron. J. 128: 105535 (2022) - 2021
- [j6]Sourav Ghosh, Surajit Kumar Roy, Chandan Giri:
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets. J. Electron. Test. 37(1): 109-126 (2021) - [j5]Tapobrata Dhar
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets. ACM J. Emerg. Technol. Comput. Syst. 17(3): 33:1-33:22 (2021) - [j4]Dilip Kumar Maity
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1500-1510 (2021) - 2020
- [c24]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. ISDCS 2020: 1-6 - [c23]Priyanka Naskar, Tapobrata Dhar, Surajit Kumar Roy:
Hardware Trojan Detection Using Improved Testability Measures. ISDCS 2020: 1-6
2010 – 2019
- 2019
- [j3]Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J. Electron. Test. 35(5): 741-759 (2019) - [c22]Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri:
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip. ATS 2019: 147-152 - [c21]Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Hardware Trojan Detection by Stimulating Transitions in Rare Nets. VLSID 2019: 537-538 - 2018
- [c20]Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Identification of Faulty TSV with a Built-In Self-Test Mechanism. ATS 2018: 1-6 - [c19]Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs. VDAT 2018: 173-185 - [c18]Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. VLSID 2018: 109-114 - 2017
- [c17]Sudeep Ghosh
TSV repairing for 3D ICs using redundant TSV. ISED 2017: 1-5 - [c16]Surajit Kumar Roy, Chandan Giri
Design-for-test and test time optimization for 3D SOCs. ITC 2017: 1-10 - [c15]Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri
Modeling and Analysis of Transient Heat for 3D IC. VDAT 2017: 365-375 - [c14]Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Faulty TSVs Identification in 3D IC Using Pre-bond Testing. VDAT 2017: 805-812 - 2016
- [j2]Surajit Kumar Roy, Chandan Giri
Optimization of Test Wrapper for TSV Based 3D SOCs. J. Electron. Test. 32(5): 511-529 (2016) - 2015
- [j1]Surajit Kumar Roy, Chandan Giri
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. IET Comput. Digit. Tech. 9(5): 268-274 (2015) - [c13]Sumit Dhuwalia, Nikhil Khemka, Prince Gupta, Surajit Kumar Roy, Chandan Giri
Test Time Optimization for 3D-SICs Having Multiple Towers. iNIS 2015: 131-136 - [c12]Surajit Kumar Roy, Kaustav Roy, Chandan Giri
Recovery of faulty TSVs in 3D ICs. ISQED 2015: 533-536 - [c11]Surajit Kumar Roy, Supriyo Mandal
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. VLSI-SoC 2015: 122-127 - 2014
- [c10]Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman
Session Based Core Test Scheduling for 3D SOCs. ISVLSI 2014: 196-201 - 2013
- [c9]Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. 3DIC 2013: 1-6 - [c8]Surajit Kumar Roy, Chandan Giri
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. IDT 2013: 1-3 - [c7]Surajit Kumar Roy, Joy Sankar Sengupta, Chandan Giri
Power constraints test scheduling of 3D stacked ICs. IDT 2013: 1-6 - 2012
- [c6]Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing. ISED 2012: 162-166 - [c5]Surajit Kumar Roy, Dona Roy, Chandan Giri
Testing 3D stacked ICs for post-bond partial/complete stack. MWSCAS 2012: 522-525 - [c4]Surajit Kumar Roy, Dona Roy, Chandan Giri
Post-bond Stack Testing for 3D Stacked IC. VDAT 2012: 59-68 - 2011
- [c3]Surajit Kumar Roy, Chandan Giri
Optimization of Test Wrapper for TSV Based 3D SOCs. ISED 2011: 188-193 - [c2]Surajit Kumar Roy, Chandan Giri
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED 2011: 230-235 - [c1]Surajit Kumar Roy, Chandan Giri
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. ISVLSI 2011: 31-36
Coauthor Index
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last updated on 2024-04-24 23:04 CEST by the dblp team
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