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David W. Boerstler
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2010 – 2019
- 2015
- [j7]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - 2014
- [c8]Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. ISSCC 2014: 98-99 - 2013
- [j6]John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai:
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. IBM J. Res. Dev. 57(6) (2013) - [c7]Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot:
On-chip circuit for measuring multi-GHz clock signal waveforms. VTS 2013: 1-4
2000 – 2009
- 2007
- [c6]Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino:
Implementation of the 65nm Cell Broadband Engine. CICC 2007: 717-720 - [c5]Fadi H. Gebara, Jeremy D. Schaub, Tuyet Nguyen, Jarom Peña, Ivan Vo, David Boerstler, Kevin J. Nowka
:
A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology. ISSCC 2007: 312-313 - 2006
- [j5]Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006) - [c4]Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto:
A new test and characterization scheme for 10+ GHz low jitter wide band PLL. ASP-DAC 2006: 856-859 - [c3]Eskinder Hailu, David W. Boerstler, Kazuhiko Miki, Jieming Qi, Michael Wang, Mack W. Riley:
A Circuit for Reducing Large Transient Current Effects on Processor Power Grids. ISSCC 2006: 2238-2245 - 2001
- [j4]Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie:
A clock distribution network for microprocessors. IEEE J. Solid State Circuits 36(5): 792-799 (2001) - 2000
- [c2]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717
1990 – 1999
- 1999
- [j3]David W. Boerstler:
A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz. IEEE J. Solid State Circuits 34(4): 513-519 (1999) - 1998
- [j2]Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33(11): 1600-1608 (1998) - [c1]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka
Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23 - 1992
- [j1]Nancy R. Aulet, David W. Boerstler, George DeMario, Frank D. Ferraiolo, Curtis E. Hayward, Charles D. Heath, Allen L. Huffman, William R. Kelly, Gerald W. Peterson, Daniel J. Stigliani Jr.:
IBM Enterprise Systems multimode fiber optic technology. IBM J. Res. Dev. 36(4): 553-576 (1992)
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