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David Hogenmiller
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2010 – 2019
- 2018
- [j2]Christopher J. Gonzalez
, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench:
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - 2017
- [c6]Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC 2017: 50-51 - 2015
- [j1]Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny:
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59(1) (2015) - [c5]David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot:
Resonant clock mega-mesh for the IBM z13TM. VLSIC 2015: 322- - 2014
- [c4]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - [c3]Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC 2014: 96-97 - [c2]Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich:
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. ISSCC 2014: 100-101 - 2013
- [c1]Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot:
On-chip circuit for measuring multi-GHz clock signal waveforms. VTS 2013: 1-4
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