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Koichi Hamashita
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2020 – today
- 2021
- [c20]Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes:
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. A-SSCC 2021: 1-3 - 2020
- [j15]Hyuk Sun
, Kazuki Sobue
A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. IEEE J. Solid State Circuits 55(2): 426-438 (2020) - [c19]Shota Konno
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. A-SSCC 2020: 1-2
2010 – 2019
- 2019
- [j14]Ahmed ElShater
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier. IEEE J. Solid State Circuits 54(12): 3410-3420 (2019) - [c18]Ahmed ElShater, Calvin Yoji Lee, Praveen Kumar Venkatachala, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier. ISSCC 2019: 70-72 - 2018
- [j13]Mahmoud Sadollahi
An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 61-73 (2018) - [j12]Hyuk Sun
An Oversampling Stochastic ADC Using VCO-Based Quantizers. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4037-4050 (2018) - [c17]Takato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita:
A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. VLSI Circuits 2018: 205-206 - 2017
- [c16]Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon:
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. CICC 2017: 1-4 - [c15]Yi Zhang, Chia-Hung Chen, Tao He, Kazuki Sobue, Koichi Hamashita, Gabor C. Temes:
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. CICC 2017: 1-4 - 2016
- [c14]Hyuk Sun, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers. A-SSCC 2016: 325-328 - [c13]Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter. ISCAS 2016: 2755-2758 - 2015
- [c12]Xin Meng, Jinzhou Cao, Tao He, Yi Zhang, Gabor C. Temes, Mitsuru Aniya, Kazuki Sobue, Koichi Hamashita:
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. ESSCIRC 2015: 221-224 - 2014
- [j11]Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. IEEE J. Solid State Circuits 49(2): 416-425 (2014) - [c11]Hariprasath Venkatram, Taehwan Oh, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. VLSIC 2014: 1-2 - 2013
- [c10]Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
Parallel gain enhancement technique for switched-capacitor circuits. CICC 2013: 1-4 - [c9]Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. ISSCC 2013: 282-283 - 2012
- [j10]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Ring Amplifiers for Switched Capacitor Circuits. IEEE J. Solid State Circuits 47(12): 2928-2942 (2012) - [c8]Shuichi Fukuda, Shinji Miya, Miho Io, Koichi Hamashita, Bram Nauta
Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure. ESSCIRC 2012: 53-56 - [c7]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Ring amplifiers for switched-capacitor circuits. ISSCC 2012: 460-462 - [c6]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. VLSIC 2012: 32-33 - 2011
- [j9]Omid Rajaee, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon:
Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. IEEE J. Solid State Circuits 46(11): 2458-2468 (2011) - [c5]Sanghyeon Lee, Jeongseok Chae
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. CICC 2011: 1-4 - [c4]Benjamin P. Hershberg, Skyler Weaver, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Binary Access Memory: An optimized lookup table for successive approximation applications. ISCAS 2011: 1620-1623 - 2010
- [j8]Yoshio Nishida, Koichi Hamashita, Gabor C. Temes:
An Enhanced Dual-Path DeltaSigma A/D Converter. IEICE Trans. Electron. 93-C(6): 884-892 (2010) - [j7]Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. IEEE J. Solid State Circuits 45(2): 368-379 (2010) - [j6]Omid Rajaee, Tawfiq Musah
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. IEEE J. Solid State Circuits 45(4): 719-730 (2010) - [c3]Jeongseok Chae
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. CICC 2010: 1-4
2000 – 2009
- 2009
- [j5]Kyehyung Lee, Qingdong Meng, Tetsuro Sugimoto, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Un-Ku Moon, Gabor C. Temes:
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. IEEE J. Solid State Circuits 44(3): 916-927 (2009) - [j4]Yusuke Aiba, Koji Tomioka, Yuta Nakashima, Koichi Hamashita, Bang-Sup Song:
A Fifth-Order Gm-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range. IEEE J. Solid State Circuits 44(9): 2381-2391 (2009) - [j3]Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon:
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. IEEE J. Solid State Circuits 44(9): 2392-2401 (2009) - [c2]Junpei Kamiishi, Yun-Shiang Shu, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. CICC 2009: 9-12 - 2008
- [j2]Kyehyung Lee, Jeongseok Chae
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. IEEE J. Solid State Circuits 43(12): 2601-2612 (2008) - [c1]Kyehyung Lee, Jeongseok Chae
A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. ISSCC 2008: 494-495 - 2005
- [j1]Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon:
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. IEEE J. Solid State Circuits 40(12): 2398-2407 (2005)
Coauthor Index
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