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Siladitya Dey 0002
Person information
- affiliation: Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA
Other persons with the same name
- Siladitya Dey 0001 — University of California, Santa Barbara, Department of Computer Science
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2020 – today
- 2021
- [c6]Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes:
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. A-SSCC 2021: 1-3 - 2020
- [j5]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey
, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55(3): 706-718 (2020)
2010 – 2019
- 2019
- [j4]Hamidreza Maghami
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2440-2453 (2019) - [c5]Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. CICC 2019: 1-4 - [c4]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC 2019: 1-4 - 2018
- [j3]Siladitya Dey
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53(3): 799-813 (2018) - [j2]Pedram Payandehnia
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2353-2364 (2018) - 2017
- [c3]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC 2017: 1-4 - 2015
- [j1]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram:
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50(8): 1833-1847 (2015) - [c2]Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu:
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC 2015: 256- - 2014
- [c1]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC 2014: 1-4
Coauthor Index
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