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Yun-Shiang Shu
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2020 – today
- 2022
- [c15]Ayman Shabra, Yun-Shiang Shu, Shon-Hang Wen, Kuan-Dar Chen:
Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters. CICC 2022: 1-8 - [c14]Yun-Shiang Shu:
Introduction of Noise-Shaping SAR ADCs. VLSI-DAT 2022: 1 - 2021
- [c13]Youngcheol Chae, Yun-Shiang Shu, Jens Anders, Viola Schaffer, Takashi Oshima
, Marco Corsi:
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits. ISSCC 2021: 517-519 - 2020
- [c12]Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh:
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. ISSCC 2020: 154-156 - [c11]Yun-Shiang Shu, Zhi-Xin Chen, Yu-Hong Lin, Su-Hao Wu, Wei-Hsiang Huang, Albert Yen-Chih Chiou, Chang-Yang Huang, Hung-Yi Hsieh, Fan-Wei Liao, Teng-Feng Zou, Ping Chen:
26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices. ISSCC 2020: 400-402
2010 – 2019
- 2019
- [c10]Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu:
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS. ISSCC 2019: 334-336 - [c9]Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu:
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range. VLSI Circuits 2019: 70- - 2016
- [j4]Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo:
An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS. IEEE J. Solid State Circuits 51(12): 2928-2940 (2016) - [c8]Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo:
27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS. ISSCC 2016: 458-459 - 2015
- [c7]Liang-Ting Kuo, Chun-Chih Hou, Meng-Hsuan Wu, Yun-Shiang Shu:
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring. A-SSCC 2015: 1-4 - 2013
- [c6]Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer. ISSCC 2013: 268-269 - [c5]Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A background calibration technique for fully dynamic flash ADCs. VLSI-DAT 2013: 1-4 - 2012
- [c4]Yun-Shiang Shu:
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators. VLSIC 2012: 26-27 - 2010
- [j3]Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. IEEE J. Solid State Circuits 45(2): 368-379 (2010)
2000 – 2009
- 2009
- [j2]Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain:
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration. IEEE J. Solid State Circuits 44(9): 2356-2365 (2009) - [c3]Junpei Kamiishi, Yun-Shiang Shu, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. CICC 2009: 9-12 - 2008
- [j1]Yun-Shiang Shu, Bang-Sup Song:
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering. IEEE J. Solid State Circuits 43(2): 342-350 (2008) - [c2]Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain:
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration. CICC 2008: 157-160 - [c1]Yun-Shiang Shu, Bang-Sup Song, Kantilal Bacrania:
A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection. ISSCC 2008: 500-501
Coauthor Index
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