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Michael S. Floyd
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2020 – today
- 2021
- [c15]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42
2010 – 2019
- 2018
- [j13]L. Baba Arimilli, Bart Blaner, Ben C. Drerup, Charles F. Marino, Derek Williams, Eric N. Lais, Francesco A. Campisano, Guy L. Guthrie, Michael S. Floyd, Ross Leavens, Scot M. Willenborg, Ronald N. Kalla, Bülent Abali:
IBM POWER9 processor and system features for computing in the cognitive era. IBM J. Res. Dev. 62(4/5): 1:1-1:11 (2018) - [j12]Christopher J. Gonzalez
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - [c14]Christos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. ISSCC 2018: 300-302 - 2017
- [c13]Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC 2017: 50-51 - [c12]Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran
26.2 Power supply noise in a 22nm z13™ microprocessor. ISSCC 2017: 438-439 - [c11]Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis:
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC 2017: 444-445 - 2015
- [j11]Manoj Dusanapudi, S. Fields, Michael S. Floyd, Guy L. Guthrie, Ronald N. Kalla, Shakti Kapoor, L. S. Leitner, Charles F. Marino, Joseph McGill, Amir Nahir, Kevin Reick, H. Shen, K. L. Wright:
Debugging post-silicon fails in the IBM POWER8 bring-up lab. IBM J. Res. Dev. 59(1) (2015) - [j10]Tobias Webel, Preetham M. Lobo, Ramon Bertran
Robust power management in the IBM z13. IBM J. Res. Dev. 59(4/5) (2015) - [c10]Yazhou Zu, Charles R. Lefurgy, Jingwen Leng, Matthew Halpern, Michael S. Floyd, Vijay Janapa Reddi:
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. MICRO 2015: 308-321 - 2013
- [j9]Michael S. Floyd, Alan J. Drake, Nicole S. Schwartz, Robert W. Berry, Charles Lefurgy, Malcolm S. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, Ruby M. Zgabay:
Runtime power reduction capability of the IBM POWER7+ chip. IBM J. Res. Dev. 57(6) (2013) - [j8]Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry:
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. IEEE Micro 33(4): 35-45 (2013) - [c9]Alan J. Drake, Michael S. Floyd, Richard L. Willaman, Derek J. Hathaway, Joshua Hernandez, Crystal Soja, Marshall D. Tiner, Gary D. Carpenter, Robert M. Senger:
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. ISLPED 2013: 193-198 - [c8]Bishop Brock, Srinivasan Ramani, Ken Vu, Heather Hanson, Michael S. Floyd:
Virtual Power Management simulation framework for computer systems. ISPASS 2013: 128-129 - 2012
- [c7]Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael S. Floyd, Karthick Rajamani, Malcolm Allen-Ware, Bishop Brock:
Accurate Fine-Grained Processor Power Proxies. MICRO 2012: 224-234 - [c6]Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Peña:
Voltage droop reduction using throttling controlled by timing margin feedback. VLSIC 2012: 96-97 - 2011
- [j7]Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez:
Adaptive energy-management features of the IBM POWER7 chip. IBM J. Res. Dev. 55(3): 8 (2011) - [j6]Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu:
Introducing the Adaptive Energy Management Features of the Power7 Chip. IEEE Micro 31(2): 60-75 (2011) - [c5]Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter:
Active management of timing guardband to save energy in POWER7. MICRO 2011: 1-11 - 2010
- [j5]Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd:
Power7: IBM's Next-Generation Server Processor. IEEE Micro 30(2): 7-15 (2010) - [c4]Michael S. Floyd, Bishop Brock, Malcolm S. Ware, Karthick Rajamani, Alan J. Drake, Charles Lefurgy, Lorena Pesantez:
Adaptive energy management features of the POWER7TM processor. Hot Chips Symposium 2010: 1-18 - [c3]Malcolm S. Ware, Karthick Rajamani, Michael S. Floyd, Bishop Brock, Juan C. Rubio, Freeman L. Rawson III, John B. Carter:
Architecting for power management: The IBM POWER7TM approach. HPCA 2010: 1-11
2000 – 2009
- 2008
- [j4]Kevin Reick, Pia N. Sanda, Scott B. Swaney, Jeffrey W. Kellington, Michael J. Mack, Michael S. Floyd, Daniel Henderson:
Fault-Tolerant Design of the IBM Power6 Microprocessor. IEEE Micro 28(2): 30-38 (2008) - 2007
- [j3]Michael S. Floyd, Soraya Ghiasi, Tom W. Keller, Karthick Rajamani, Freeman L. Rawson III, Juan C. Rubio, Malcolm S. Ware:
System power management support in the IBM POWER6 microprocessor. IBM J. Res. Dev. 51(6): 733-746 (2007) - [j2]Hye-Young McCreary, Martha A. Broyles, Michael S. Floyd, Andrew J. Geissler, Steven P. Hartman, Freeman L. Rawson III, Todd J. Rosedahl, Juan C. Rubio, Malcolm S. Ware:
EnergyScale for IBM POWER6 microprocessor-based systems. IBM J. Res. Dev. 51(6): 775-786 (2007) - [c2]Alan J. Drake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman K. James, Michael S. Floyd, Vikas Pokala:
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. ISSCC 2007: 398-399 - 2004
- [c1]Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson:
Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672 - 2002
- [j1]Douglas C. Bossen, Alongkorn Kitamorn, Kevin Reick, Michael S. Floyd:
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology. IBM J. Res. Dev. 46(1): 77-86 (2002)
Coauthor Index
aka: Malcolm S. Ware
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