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Masashi Tawada
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2020 – today
- 2024
- [j15]Siya Bao
, Masashi Tawada
An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. IEEE Trans. Consumer Electron. 70(1): 445-459 (2024) - [c24]Yui Tsuyumine, Kenichi Masuda, Takeshi Hachikawa, Tsuyoshi Haga, Yuta Yachi, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa:
Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. ICCE 2024: 1-5 - [c23]Yuta Atobe, Masashi Tawada, Nozomu Togawa:
A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting. MWSCAS 2024: 1154-1157 - 2023
- [j14]Yuta Yachi, Masashi Tawada, Nozomu Togawa:
An Efficient Combined Bit-Width Reducing Method for Ising Models. IEICE Trans. Inf. Syst. 106(4): 495-508 (2023) - [c22]Yuta Yachi, Masashi Tawada, Nozomu Togawa:
A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. SOCC 2023: 1-6 - 2022
- [j13]Daisuke Oku
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers 71(1): 223-234 (2022) - [j12]Yuta Atobe
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. IEEE Trans. Computers 71(10): 2606-2619 (2022) - [c21]Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa:
Efficient Coefficient Bit-Width Reduction Method for Ising Machines. ICCE 2022: 1-6 - [c20]Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa:
QUBO Matrix Distorting Method for Consumer Applications. ICCE 2022: 1-6 - 2021
- [j11]Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa:
Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. IEICE Trans. Inf. Syst. 104-D(4): 481-489 (2021) - [c19]Shota Matsuno, Masashi Tawada, Nozomu Togawa
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ICCE 2021: 1-6 - [c18]Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
Multi-day Travel Planning Using Ising Machines for Real-world Applications. ITSC 2021: 3704-3709 - [c17]Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. VLSI-DAT 2021: 1-4 - 2020
- [j10]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13: 10-20 (2020) - [c16]Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC 2020: 11-12 - [c15]Masashi Tawada, Shu Tanaka, Nozomu Togawa
A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. ICCE 2020: 1-6 - [c14]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS 2020: 1-4 - [c13]Masashi Tawada, Nozomu Togawa
Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. NEWCAS 2020: 271-274
2010 – 2019
- 2019
- [c12]Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. ICCE-Berlin 2019: 227-232 - [c11]Sho Kanamaru, Daisuke Oku
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE 2019: 1-6 - [c10]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS 2019: 578-581 - [c9]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS 2019: 243-246 - [c8]Yuta Ideguchi, Norifumi Kamiya
Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. MWSCAS 2019: 981-984 - 2018
- [j9]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1002-1013 (2018) - [j8]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1045-1052 (2018) - [c7]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS 2018: 53-56 - [c6]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS 2018: 182-185 - 2017
- [c5]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
Effective write-reduction method for MLC non-volatile memory. ISCAS 2017: 1-4 - 2016
- [j7]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2398-2411 (2016) - 2015
- [j6]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2484-2493 (2015) - [j5]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2494-2504 (2015) - [c4]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC 2015: 496-501 - [c3]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD 2015: 682-689 - 2014
- [c2]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS 2014: 304-307 - 2013
- [j4]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1283-1292 (2013) - [c1]Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON 2013: 1-4 - 2011
- [j3]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express 8(14): 1161-1167 (2011) - [j2]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6(4): 1076-1091 (2011) - [j1]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 166-181 (2011)
Coauthor Index
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