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A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E96-A No.6 pp.1283-1292 Publication Date: 2013/06/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E96.A.1283 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: cache simulation, optimaize cache memory, multicore cache, Full Text: PDF(1.4MB)>>
Summary: Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach. | ||||||||||
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