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ACM Transactions on Design Automation of Electronic Systems, Volume 18
Volume 18, Number 1, December 2012
- Ayse Kivilcim Coskun, Yung-Hsiang Lu, Qinru Qiu:
Introduction to the special section on adaptive power management for energy and temperature-aware computing systems. 1:1-1:2 - Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig
, Moritz Schmid, Jürgen Teich:
Hierarchical power management for adaptive tightly-coupled processor arrays. 2:1-2:25 - Meeta Srivastav, Michael B. Henry, Leyla Nazhandali:
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage. 3:1-3:23 - Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao
A self-tuning design methodology for power-efficient multi-core systems. 4:1-4:24 - Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing. 5:1-5:23 - Francesco Zanini, David Atienza, Colin N. Jones, Luca Benini
Online thermal control methods for multiprocessor systems. 6:1-6:26 - Ryan Cochran, Sherief Reda:
Thermal prediction and adaptive control through workload phase detection. 7:1-7:19 - Liang Shi, Jianhua Li, Chun Jason Xue
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems. 8:1-8:23 - Amit Kumar Singh, Akash Kumar
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs. 9:1-9:29 - Kalyan Saladi, Harikumar Somakumar, Mahadevan Ganapathi:
Concurrency-aware compiler optimizations for hardware description languages. 10:1-10:16 - Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. 11:1-11:35 - Masanori Kurimoto, Takeshi Yamamoto, Satoshi Nakano, Atsuto Hanami, Hiroyuki Kondo:
Verification work reduction methodology in low-power chip implementation. 12:1-12:15 - Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. 13:1-13:18 - Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
Using implications to choose tests through suspect fault identification. 14:1-14:19 - Santiago Mok, John Lee, Puneet Gupta
Discrete sizing for leakage power optimization in physical design: A comparative study. 15:1-15:11 - John Lee, Puneet Gupta
ECO cost measurement and incremental gate sizing for late process changes. 16:1-16:11
Volume 18, Number 2, March 2013
- George Kornaros
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip. 17:1-17:38 - Rico Backasch, Christian Hochberger, Alexander Weiss, Martin Leucker
Runtime verification for multicore SoC with high-quality trace data. 18:1-18:26 - José C. Costa, José C. Monteiro
Coverage-directed observability-based validation for embedded software. 19:1-19:20 - Chun-An Chen, Sun-Yuan Hsieh:
t/t-Diagnosability of regular graphs under the PMC model. 20:1-20:13 - Chen Huang, Bailey Miller, Frank Vahid, Tony Givargis:
Synthesis of networks of custom processing elements for real-time physical system emulation. 21:1-21:21 - Domenic Forte
Resource-aware architectures for adaptive particle filter based visual target tracking. 22:1-22:27 - Baoxian Zhao, Hakan Aydin, Dakai Zhu
Shared recovery for energy efficiency and reliability enhancements in real-time applications with precedence constraints. 23:1-23:21 - Hao Shen, Ying Tan, Jun Lu, Qing Wu, Qinru Qiu:
Achieving autonomous power management using reinforcement learning. 24:1-24:32 - Jongwon Lee, Jonghee M. Youn
Reducing instruction bit-width for low-power VLIW architectures. 25:1-25:32 - Mehrdad Majzoobi, Joonho Kong, Farinaz Koushanfar
Low-power resource binding by postsilicon customization. 26:1-26:22 - Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan:
Low-power anti-aging zero skew clock gating. 27:1-27:37 - Hai Wang, Sheldon X.-D. Tan, Duo Li, Ashish Gupta, Yuan Yuan:
Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors. 28:1-28:27 - Zhiyu Zeng, Suming Lai, Peng Li:
IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications. 29:1-29:21 - Ren-Jie Lee, Hung-Ming Chen:
A study of row-based area-array I/O design planning in concurrent chip-package design flow. 30:1-30:19 - Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
Revisiting automated physical synthesis of high-performance clock networks. 31:1-31:27 - Michael Gester, Dirk Müller, Tim Nieberg, Christian Panten, Christian Schulte, Jens Vygen:
BonnRoute: Algorithms and data structures for fast and good VLSI routing. 32:1-32:24 - Amit Agarwal, Jason Cong, Brian Tagiku:
The survivability of design-specific spare placement in FPGA architectures with high defect rates. 33:1-33:22
Volume 18, Number 3, July 2013
- Raj Rao Nadakuditi
On bottleneck analysis in stochastic stream processing. 34:1-34:20 - Fatma Abouelella, Tom Davidson, Wim Meeus, Karel Bruneel, Dirk Stroobandt:
How to efficiently implement dynamic circuit specialization systems. 35:1-35:38 - Gianpiero Cabodi, Sergio Nocco, Stefano Quer
Thread-based multi-engine model checking for multicore platforms. 36:1-36:28 - Sehwan Kim, Pai H. Chou:
Analysis and minimization of power-transmission loss in locally daisy-chained systems by local energy buffering. 37:1-37:16 - Saket Gupta, Sachin S. Sapatnekar
Employing circadian rhythms to enhance power and reliability. 38:1-38:23 - Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu:
Routability optimization for crossbar-switch structured ASIC design. 39:1-39:28 - Shih-Ying Sean Liu, Wan-Ting Lo, Chieh-Jui Lee, Hung-Ming Chen:
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization. 40:1-40:20 - Yu-Min Lee, Pei-Yu Huang:
An efficient method for analyzing on-chip thermal reliability considering process variations. 41:1-41:32 - Yiyu Shi, Jinjun Xiong
Order statistics for correlated random variables and its application to at-speed testing. 42:1-42:20 - Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-safe application of tdf patterns to flip-chip designs during wafer test. 43:1-43:20 - Dong Xiang, Jianbo Li, Krishnendu Chakrabarty
Test compaction for small-delay defects using an effective path selection scheme. 44:1-44:23
Volume 18, Number 4, October 2013
- Diana Marculescu
Editorial to special section on networks on chip: Architecture, tools, and methodologies. 45:1-45:2 - Paul Bogdan
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach. 46:1-46:20 - Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. 47:1-47:21 - Jaekyu Lee
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures. 48:1-48:28 - Ahmed Abousamra
Ordering circuit establishment in multiplane NoCs. 49:1-49:33 - Jinho Lee
Deflection routing in 3D network-on-chip with limited vertical bandwidth. 50:1-50:22 - Hamid Shojaei, Twan Basten
A fast and scalable multidimensional multiple-choice knapsack heuristic. 51:1-51:32 - Jonghee W. Yoon, Jongeun Lee, Sanghyun Park, Yongjoo Kim, Jinyong Lee, Yunheung Paek, Doosan Cho:
Architecture customization of on-chip reconfigurable accelerators. 52:1-52:22 - Reiley Jeyapaul
Enabling energy efficient reliability in embedded systems through smart cache cleaning. 53:1-53:25 - Ismail Kadayif, Mahir Turkcan, Seher Kiziltepe, Ozcan Ozturk:
Hardware/software approaches for reducing the process variation impact on instruction fetches. 54:1-54:23 - Guanying Wu, Xubin He, Ningde Xie, Tong Zhang:
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes. 55:1-55:22 - Po-Chun Huang, Yuan-Hao Chang
An index-based management scheme with adaptive caching for huge-scale low-cost embedded flash storages. 56:1-56:26 - Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li:
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices. 57:1-57:18 - Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel differential scan attack on advanced DFT structures. 58:1-58:22 - Yao-Lin Chang, I-Lun Tseng:
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons. 59:1-59:18 - Rohit Sunkam Ramanujam, Bill Lin:
Destination-based congestion awareness for adaptive routing in 2D mesh networks. 60:1-60:27 - Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong
A routing algorithm for graphene nanoribbon circuit. 61:1-61:18
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