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SoCC 2005: Herndon, VA, USA
- Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA. IEEE 2005, ISBN 0-7803-9264-7
Frequency Synthesizers and Generators
- Sangho Shin, Kwyro Lee, Sung-Mo Kang:
3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance. 1-6 - Ram Kelkar, Dave Flye, Anjali Malladi, Joseph Natonio, Chri Scoville, Ken Short, Pradeep Thiagarajan:
A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications. 7-10 - Sung-Sop Lee, Hyung-Wook Jang, Jin-Ku Kang:
3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling. 11-14 - Sanjay Kumar Wadhwa, Qadeer Ahmad Khan, Kulbhushan Misri, Deeya Muhury:
Digital clock frequency doubler. 15-18
Physical and Micro-Architecture Design Methods
- Zhengtao Yu, Xun Liu:
Power minimization of rotary clock design. 19-24 - Charles Addo-Quaye:
Thermal-aware mapping and placement for 3-D NoC designs. 25-28 - Jun Cheng Chi, Tsung Hui Huang, Mely Chen Chi:
An IR drop-driven placer for standard cells in a SOC design. 29-32 - Huibin Shi, Chris Bailey, Glenn Farrall, Neil Hastie, Sam Jenkins:
Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture. 33-36
Analog Design for SoC
- Chih-Peng Liu, Han-Pang Huang:
A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current Compensation. 37-42 - Chih-Peng Liu, Han-Pang Huang:
Hybrid Voltage and Current References Based on Double ZTC Points. 43-46 - Chung-Yuan Chen, Tai-Ping Sun:
Automatic gain control circuit for power line communication application. 47-50 - José Camargo da Costa, Adson Ferreira da Rocha, Leonardo R. A. X. de Menezes, Ricardo Pezzuol Jacobi, Alexandre R. S. Romariz, R. R. P. Soares, Gilmar S. Beserra, J. D. Costa, Genival Mariano de Araujo, W. A. Araujo, J. C. Sd. S. Marra, W. A. Amaral, P. R. O. Vogel, A. L. da Silva, A. Jd. O. Martins, L. R. Povoa:
CMOS SoC for irrigation control. 51-54
DFT and Test Structures
- Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi:
A Flow Graph Technique for DFT Controller Modification. 55-60 - Cleonilson Protásio de Souza, Raimundo Carlos Silvério Freire, Francisco Marcos de Assis:
Testing system-on-a-chip using artificial immune system. 61-64 - Hamidreza Hashempour, Fabrizio Lombardi:
Improving Error Resilience for Compressed Test Sets by Don't Care Assignment. 65-68 - Sangwook Cho, Jaehoon Song, Hyunbean Yi, Sungju Park:
Hybrid test data compression technique for SOC scan testing. 69-72
Poster Session
- Larry Li, Hou-Ming Chen, Robert Chen-Hao Chang:
A low jitter delay-locked loop with a realignment duty cycle corrector. 73-76 - Hai Qi Liu, Wang Ling Goh, Liter Siek
:
1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology. 77-78 - Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye:
A CMOS RF tuning wide-band bandpass filter for wireless applications. 79-80 - Jacob R. Minz, Eric Wong, Sung Kyu Lim:
Reliability-aware floorplanning for 3D circuits. 81-82 - Anders Edman, Christer Svensson, Behzad Mesgarzadeh:
Synchronous latency-insensitive design for multiple clock domain. 83-86 - Jun-Hee Mun, Muling Peng, Sangjin Hong, Alex Doboli, K. Wendy Tang:
Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture. 87-88 - Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Özcan Özturk:
Constraint-based Code mapping for heterogeneous Chip multiprocessors. 89-90 - Tiago Dias
Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding. 91-92 - Cheng Zhan, Sami Khawam, Tughrul Arslan, Iain Lindsay:
Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications. 93-94 - Ramy E. Aly, Magdy A. Bayoumi:
Precharged SRAM cell for ultra low-power on-chip cache. 95-98 - Sookyoung Kim, Thomas L. Martin:
GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systems. 99-100 - Michael Wieckowski, Martin Margala:
A novel five-transistor (5T) sram cell for high performance cache. 101-102 - Imran Ahmed, Tughrul Arslan, Sajid Baloch:
Improved memory strategy for logmap turbo decoders. 103-104 - Suman K. Banerjee, Radu M. Secareanu, Eric Nabity, Alain Duvallet, Olin L. Hartin:
Accurate Simulation Environment for Signal Isolation in Mixed-Signal Design. 105-108 - Paolo Gai, Giuseppe Lipari
Support for multiprocessor synchronization and resource sharing in system-on-programmable chips with softcores. 109-110 - Akshay Athalye, Sangjin Hong:
Mapping of partial reconfigurable data flows to Xilinx FPGAs. 111-112 - Zhenyu Liu, Tughrul Arslan, Sami Khawam, Ahmet T. Erdogan
A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines. 113-114 - Hongyan Yang, Sotirios G. Ziavras:
FPGA-based vector processor for algebraic equation solvers. 115-116 - Xiang Li, Rahul Chopra, Kenneth W. Hsu:
Novel VLSI architecture of motion estimation for H.264 standard. 117-118
SoC Architecture and Design Methods
- Thomas Zeitlhofer, Bernhard Wess:
Integrated assignment of registers and functional units for heterogeneous vliw-architectures. 119-124 - Suresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Narayanan Vijaykrishnan:
Simultaneous memory and bus partitioning for SoC architectures. 125-128 - Tiberiu Seceleanu, Ville Leppänen
Resource allocation methodology for the segmented bus platform. 129-132 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
System Level Design Methodology for System On Chips using Multi-Threaded Graphs. 133-136
Low Power Design
- Ajay Joshi, Jeffrey A. Davis:
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing. 137-142 - Raghavan Ramadoss:
A New Breed of Power-Aware Hybrid Shifters. 143-146 - Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka:
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength. 147-150 - Zhiyu Liu, Volkan Kursun
Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling. 151-154
Embedded Systems, Sensors and Mems
- Sri Hari Krishna Narayanan, Özcan Özturk, Mahmut T. Kandemir, Mustafa Karaköy:
Workload Clustering for Increasing Energy Savings on Embedded MPSoCs. 155-160 - Faisal Mohd-Yasin
Design and implementation of interface circuitry for cmos-based saw gas sensors. 161-164
Low Power Memory
- Praveen Elakkumanan, Charan Thondapu, Ramalingam Sridhar:
DG-SRAM: a low leakage memory circuit. 167-170 - Ramy E. Aly, Md. Ibrahim Faisal, Magdy A. Bayoumi:
Novel 7T sram cell for low power cache design. 171-174 - Özcan Özturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun:
On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression. 175-178
Radio Frequency and Optical Circuits
- Woochul Jeon, John Melngailis, Robert W. Newcomb:
CMOS passive RFID transponder with read-only memory for low cost fabrication. 181-184 - Ji-Hoon Kim, Hyung-Joun Yoo:
A band-switching wide-band CMOS LC QVCO for multi-standard applications. 185-188 - Yong-Seok Hwang, Sang-Sun Yoo, Hyung-Joun Yoo:
A 2 GHz and 5GHz dual-band direct conversion RF frontend for multi-standard applications. 189-192 - Paul Muller, Yusuf Leblebici:
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs. 193-196
Signal Integrity and On-Chip Interconnections
- Nan Wang, Magdy A. Bayoumi:
Dynamic fraction control bus: new SOC on-chip communication architecture design. 199-202 - Jinsook Kim, Weiping Ni, Edwin C. Kan:
Resistive Loss and Trans-Impedance Characterization of Nonlinear Transmission Lines on CMOS SOI Substrate. 203-206 - Vinita V. Deodhar, Jeffrey A. Davis:
Designing for signal integrity in wave-pipelined SOC global interconnects. 207-210 - Soo Yun Hwang, Kyoung-Sun Jhang:
An improved implementation method of AHB BusMatrix. 211-214
High-End SoC Challenges 1: From IP Reuse to Sign-Off
- Soujanna Sarkar, Subash Chandar G., Sanjay Shinde:
Effective IP reuse for high quality SOC design. 217-224 - Thi Nguyen, Kaijian Shi:
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. 225-228 - Mariagrazia Graziano, Cristiano Forzan, Davide Pandini:
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow. 229-232
SoC Configurable Architectures and Runtime Support
- Alberto Donato, Fabrizio Ferrandi
Operating system support for dynamically reconfigurable SoC architectures. 233-238 - Alexander Thomas, Jürgen Becker:
Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment. 239-242 - Vijay K. Jain, Sanjukta Bhanja, Glenn H. Chapman, Lavanya Doddannagari:
A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC. 243-246 - Jong Hun Han, Ahmet T. Erdogan
A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems. 247-250
High-End SoC Challenges II: Design Issues
- Kaijian Shi, Hichem Belhadj:
A Clock Isolation Method For Complex SoC Designs. 251-256 - Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu:
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. 257-260 - Xufan Wu, Jun Yang, Longxing Shi:
Bus Buffer Evaluation of Different Arbitration Algorithms. 261-264
FPGAS for Security and SIMD Applications
- Bassel Soudan, Wael Adi, Abdulrahman Hanoun:
Novel secret-key IPR protection in FPGA environment. 267-270 - Abdullah AlKalbany, Hussein Ahmad Al Hassan, Magdy Saeb:
FPGA implementation of the "pyramids" block cipher. 271-275 - Xizhen Xu, Sotirios G. Ziavras:
A hierarchically-controlled SIMD machine for 2D DCT on FPGAs. 276-279
Wireless/Wireline Communication and Signal Processing
- Stephen O'Kane, Sakir Sezer, Ciaran Toal:
Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch. 283-286 - Zhaohui Liu, Kevin Dickson, John V. McCanny:
Hardware Design of Sphere Decoding for MIMO Systems. 287-290 - Andrea Molino, Fabrizio Vacca, Guido Masera:
Design and implementation of phase correlation based motion estimator. 291-294
High Performance Circuits and Systems
- Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim:
Differential Pass Transistor Pulsed Latch. 295-300 - Ashok Narasimhan, Karthik Srinivasan, Ramalingam Sridhar:
A High-Performance Router Design for VDSM NoCs. 301-304 - Amir Khatibzadeh, Kaamran Raahemifar, Majid Ahmadi:
A novel multiplier for high-speed applications. 305-308 - Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits. 309-312
Tutorial Sessions
- Adam Donlin, Jürgen Becker, Michael Hübner:
I Models and Tools for the Dynamic Reconfiguration of FPGAs. 313-316 - Travis Scheckel:
Serial RapidlO: Benefiting System Interconnects. 317-318 - Nat Seshan, Todd Hiers, Gustavo Martinez, Anthony Seely, Zoran Nikolic:
Digital signal processors for communications, video infrastructure, and audio. 319-321 - Amir Hekmatpour, Kenneth Goodnow, Hemen Shah:
Standards-compliant IP-based ASIC and SoC design. 322-323 - Himanshu Kaul:
High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS. 324
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