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SAMOS 2016: Samos Island, Greece
- Walid A. Najjar, Andreas Gerstlauer:
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016. IEEE 2016, ISBN 978-1-5090-3076-7
Keynotes
- Uri C. Weiser:
Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question. i - Alex Nicolau:
Is computer science dying? ii
Domain-specific Optimization
- Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid:
Concurrent memory subsystem and application optimization for ASIP design. 1-10 - Maria H. Rodriguez Blanco, Georg Reinke, Gerd Ascheid, Rainer Leupers:
Automatic recognition of computational kernels for platform-dependent code optimizations. 11-20 - Gustav Cedersjo, Jörn W. Janneck:
Processes and actors: Translating Kahn processes to dataflow with firing. 21-30
Power & Energy
- Connor Imes, Henry Hoffmann:
Bard: A unified framework for managing soft timing and power constraints. 31-38 - Vi Ngoc-Nha Tran, Brendan Barry, Phuong Hoai Ha
:
Power models supporting energy-efficient co-design on ultra-low power embedded systems. 39-46 - Rawlinson S. Gonçalves, Diego Q. Pinheiro, Eduardo Bezerra Valentin, Horacio A. B. F. de Oliveira, Raimundo S. Barreto
Real-time tasks and voltage/frequency controller collaboration on low power energy operational systems. 47-54
System level Performance
- Manuel Selva, Lionel Morel, Kevin Marquet:
numap: A portable library for low-level memory profiling. 55-62 - Jason Jong Kyu Park, Yongjun Park, Scott A. Mahlke:
A bypass first policy for energy-efficient last level caches. 63-70 - Yun Wu
Runtime support for adaptive power capping on heterogeneous SoCs. 71-78
Architecture/Processor level Acceleration
- Santhi Natarajan
AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators. 79-87 - Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer:
Simulator calibration for accelerator-rich architecture studies. 88-95
Simulation & Design Space Exploration
- Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung, Norbert Wehn:
Exploring system performance using elastic traces: Fast, accurate and portable. 96-105 - Nikos Nikoleris, Andreas Sandberg
CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling. 106-115 - Reena Panda, Xinnian Zheng, Shuang Song, Jee Ho Ryoo, Michael LeBeane, Andreas Gerstlauer, Lizy K. John:
Genesys: Automatically generating representative training sets for predictive benchmarking. 116-123 - Wonyong Sung, Jinhwan Park:
Architecture exploration of a programmable neural network processor for embedded systems. 124-131
System Design
- Kai Neubauer
Supporting composition in symbolic system synthesis. 132-139 - Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry:
Design productivity of a high level synthesis compiler versus HDL. 140-147 - Maria Pittou, Stavros Tripakis
Multi-view consistency for infinitary regular languages. 148-155 - Yifan He, Maurice Peemen, Luc Waeijen, Erkan Diken, Mattia Fiumara, Gerard K. Rauwerda, Henk Corporaal, Tong Geng:
A configurable SIMD architecture with explicit datapath for intelligent learning. 156-163
Performance Issues in Embedded Systems
- Naveed Ul Mustafa
Implications of non-volatile memory as primary storage for database management systems. 164-171 - Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Improving performance in VLIW soft-core processors through software-controlled scratchpads. 172-179 - Giorgis Georgakoudis
NanoStreams: Codesigned microservers for edge analytics in real time. 180-187 - Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni
Evaluating physically unclonable functions on a large set of FPGAs. 188-195
Application/Algorithm level Acceleration
- Tomasz Patyk, Jarmo Takala
Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs. 196-201 - Julius, Gopinath Mahale, T. Sumana, C. S. Adityakrishna:
On the modeling of error functions as high dimensional landscapes for weight initialization in learning networks. 202-210 - Konrad Häublein, Marc Reichenbach
Hybrid code description for developing fast and resource efficient image processing architectures. 211-218 - Nils Voss, Stephen Girdlestone, Oskar Mencer, Georgi Gaydadjiev
Automated dataflow graph merging. 219-226
Special Session on Reconfigurable Compute Architectures (RCA)
- Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. 227-234 - Mark Wijtvliet, Luc Waeijen, Henk Corporaal:
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification. 235-244 - Artur Podobas, Mats Brorsson:
Empowering OpenMP with automatically generated hardware. 245-252 - Heikki O. Kultala, Timo Viitanen
Aggressively bypassing list scheduler for transport triggered architectures. 253-260 - Michail S. Vavouras, Rui Policarpo Duarte, Antonino Armato, Christos-Savvas Bouganis
A hybrid ASIC/FPGA fault-tolerant artificial pancreas. 261-267
Special Sessionon on Circuits, Systems and Design Automation for Emerging Technologie
- Robert Wille, Anupam Chattopadhyay, Rolf Drechsler
From reversible logic to quantum circuits: Logic design for an emerging technology. 268-274 - Swaroop Ghosh, Rekha Govindaraj:
A strong arbiter PUF using resistive RAM. 275-280 - Suman Deb, Leibin Ni, Hao Yu, Anupam Chattopadhyay:
Racetrack memory-based encoder/decoder for low-power interconnect architectures. 281-287 - Max Marcel Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Transforming nanodevices to next generation nanosystems. 288-292
Special Session on European Projects on heterogeneous microservers and parallel embedded computing
- Michal Kierzynka, Ariel Oleksiak, Giovanni Agosta
Data centres for IoT applications: The M2DC approach (Invited paper). 293-299 - Ioannis Stamelos, Dimitrios Soudris, Christoforos Kachris:
Performance and energy evaluation of spark applications on low-power SoCs. 300-305 - Tobias Kalb, Lester Kalms, Diana Göhringer
TULIPP: Towards ubiquitous low-power image processing platforms. 306-311 - Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris:
Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend. 312-319 - Alessio Agneessens, Francesco Buemi, Stefano Delucchi, Massimo Massa, Giovanni Agosta
Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP project. 320-327 - Fynn Schwiegelshohn, Philipp Wehner, Florian Werner, Diana Göhringer
Enabling indoor object localization through Bluetooth beacons on the RADIO robot platform. 328-333 - Andy D. Pimentel:
Perspectives on system-level MPSoC design space exploration. 335 - Kostas Siozios
A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. 336-341 - Maria Mendez Real, Philipp Wehner, Jens Rettkowski, Vincent Migliore, Vianney Lapotre, Diana Göhringer
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures. 342-347 - Sören Schreiner, Ralph Görgen, Kim Grüttner, Wolfgang Nebel:
A quasi-cycle accurate timing model for binary translation based instruction set simulators. 348-353 - Pedro B. Campos, Nizar Dahir
XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation. 354-359 - Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis
A hybrid approach for mapping and scheduling on heterogeneous multicore systems. 360-365 - Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Stefan Schürmans:
Black box ESL power estimation for loosely-timed TLM models. 366-371 - Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. 372-377 - Ryan Marlow, Shenghou Ma, Kevin Lee, Andrew Love, Peter M. Athanas:
Incorporating rapid design assembly into a virtual prototyping environment. 378-383
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