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Magnus Jahre
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2020 – today
- 2024
- [j17]Björn Gottschall
, Lieven Eeckhout
Per-Instruction Cycle Stacks Through Time-Proportional Event Analysis. IEEE Micro 44(4): 27-33 (2024) - [c41]Fatemeh Ghasemi, Lukas Liedtke
ECM: Improving IoT Throughput with Energy-Aware Connection Management. DATE 2024: 1-6 - [c40]Joseph Rogers, Taha Soliman, Magnus Jahre:
AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures. ISCA 2024: 487-500 - [c39]Truls Asheim
CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions. SESAME@EuroSys 2024: 1-8 - 2023
- [j16]Mostafa Koraei, Juan M. Cebrian
Near-optimal multi-accelerator architectures for predictive maintenance at the edge. Future Gener. Comput. Syst. 140: 331-343 (2023) - [j15]Shiqing Zhang
Characterizing Multi-Chip GPU Data Sharing. ACM Trans. Archit. Code Optim. 20(4): 56:1-56:24 (2023) - [c38]Xia Zhao, Magnus Jahre, Yuhua Tang, Guangda Zhang, Lieven Eeckhout:
NUBA: Non-Uniform Bandwidth GPUs. ASPLOS (2) 2023: 544-559 - [c37]Björn Gottschall, Silvio Heverton Campelo de Santana, Magnus Jahre:
Balancing Accuracy and Evaluation Overhead in Simulation Point Selection. IISWC 2023: 43-53 - [c36]Fatemeh Ghasemi, Lukas Liedtke
ESS: Repeatable Evaluation of Energy Harvesting Subsystems for Industry-Grade IoT Platforms. IISWC 2023: 65-76 - [c35]Björn Gottschall
TEA: Time-Proportional Event Analysis. ISCA 2023: 23:1-23:13 - [c34]Shiqing Zhang
SAC: Sharing-Aware Caching in Multi-Chip GPUs. ISCA 2023: 43:1-43:13 - [c33]Fatemeh Ghasemi, Lukas Liedtke
PES: An Energy and Throughput Model for Energy Harvesting IoT Systems. ISPASS 2023: 13-23 - 2022
- [j14]Peter Salvesen, Magnus Jahre
LMT: Accurate and Resource-Scalable Slowdown Prediction. IEEE Comput. Archit. Lett. 21(2): 97-100 (2022) - [c32]Xia Zhao, Lieven Eeckhout, Magnus Jahre:
Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures. HPCA 2022: 1014-1028 - 2021
- [j13]Fatemeh Ghasemi
Modeling Periodic Energy-Harvesting Computing Systems. IEEE Comput. Archit. Lett. 20(2): 142-145 (2021) - [j12]Yahya H. Yassin, Magnus Jahre
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. J. Signal Process. Syst. 93(1): 33-48 (2021) - [c31]Björn Gottschall, Lieven Eeckhout, Magnus Jahre
TIP: Time-Proportional Instruction Profiling. MICRO 2021: 15-27 - 2020
- [j11]Mostafa Koraei, Omid Fatemi, Magnus Jahre
DCMI: A Scalable Strategy for Accelerating Iterative Stencil Loops on FPGAs. ACM Trans. Archit. Code Optim. 16(4): 36:1-36:24 (2020) - [j10]Juan M. Cebrian
Scalability analysis of AVX-512 extensions. J. Supercomput. 76(3): 2082-2097 (2020) - [c30]Xia Zhao, Magnus Jahre
HSM: A Hybrid Slowdown Model for Multitasking GPUs. ASPLOS 2020: 1371-1385 - [c29]Xia Zhao, Magnus Jahre
Selective Replication in Memory-Side GPU Caches. MICRO 2020: 967-980 - [c28]Lu Wang, Magnus Jahre
MDM: The GPU Memory Divergence Model. MICRO 2020: 1009-1021
2010 – 2019
- 2019
- [j9]Lu Wang
Modeling Emerging Memory-Divergent GPU Applications. IEEE Comput. Archit. Lett. 18(2): 95-98 (2019) - [i6]Magnus Själander, Magnus Jahre, Gunnar Tufte, Nico Reissmann:
EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure. CoRR abs/1912.05848 (2019) - 2018
- [c27]Ahmad Sadek
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview. ARC 2018: 737-749 - [c26]Magnus Jahre
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime. HPCA 2018: 296-309 - [c25]Yuxi Liu, Xia Zhao, Magnus Jahre
Get Out of the Valley: Power-Efficient Address Mapping for GPUs. ISCA 2018: 166-179 - 2017
- [j8]Joseph Schuchart
The READEX formalism for automatic tuning for energy efficiency. Computing 99(8): 727-745 (2017) - [c24]Yaman Umuroglu, Magnus Jahre
Towards efficient quantized neural network inference on mobile devices: work-in-progress. CASES 2017: 18:1-18:2 - [c23]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA 2017: 65-74 - [c22]Mostafa Koraei, Magnus Jahre, S. Omid Fatemi:
Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only). FPGA 2017: 287 - [c21]Mostafa Koraei, Magnus Jahre
DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications. HEART 2017: 7:1-7:11 - [c20]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC 2017: 25-30 - [c19]Peder Voldnes Langdal, Magnus Jahre
Extending OMPT to Support Grain Graphs. IWOMP 2017: 141-155 - [i5]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR abs/1701.03400 (2017) - [i4]Yaman Umuroglu, Magnus Jahre:
Streamlined Deployment for Quantized Neural Networks. CoRR abs/1709.04060 (2017) - 2016
- [j7]Yaman Umuroglu, Magnus Jahre
Random access schemes for efficient FPGA SpMV acceleration. Microprocess. Microsystems 47: 321-332 (2016) - [c18]Nico Reissmann, Thomas L. Falch, Benjamin A. Bjørnseth, Helge Bahmann, Jan Christian Meyer, Magnus Jahre
Efficient control flow restructuring for GPUs. HPCS 2016: 48-57 - [c17]Tobias Kalb, Lester Kalms, Diana Göhringer
TULIPP: Towards ubiquitous low-power image processing platforms. SAMOS 2016: 306-311 - [i3]Nico Reissmann, Jan Christian Meyer, Magnus Jahre:
A Study of Energy and Locality Effects using Space-filling Curves. CoRR abs/1606.06133 (2016) - [i2]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR abs/1612.07119 (2016) - 2015
- [j6]Juan M. Cebrian
ParVec: vectorizing the PARSEC benchmark suite. Computing 97(11): 1077-1100 (2015) - [j5]Alexandru C. Iordan, Magnus Jahre
Tuning the victim selection policy of Intel TBB. J. Syst. Archit. 61(10): 584-591 (2015) - [c16]Yaman Umuroglu, Magnus Jahre
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. ARC 2015: 15-26 - [c15]Yaman Umuroglu, Donn Morrison, Magnus Jahre
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform. FPL 2015: 1-8 - 2014
- [j4]Helge Bahmann, Nico Reissmann, Magnus Jahre
Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Trans. Archit. Code Optim. 11(4): 66:1-66:25 (2014) - [c14]Magnus Jahre
Graph-based performance accounting for chip multiprocessor memory systems. PACT 2014: 473-474 - [c13]Alexandru C. Iordan, Magnus Jahre
Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. ARCS 2014: 13-24 - [c12]Yaman Umuroglu, Magnus Jahre
An energy efficient column-major backend for FPGA SpMV accelerators. ICCD 2014: 432-439 - [c11]Nico Reissmann, Jan Christian Meyer, Magnus Jahre
A Study of Energy and Locality Effects Using Space-Filling Curves. IPDPS Workshops 2014: 815-822 - [c10]Juan M. Cebrian
Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks. ISPASS 2014: 66-75 - [c9]Nikita Nikitin, Magnus Jahre
Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis. ISVLSI 2014: 172-177 - 2013
- [c8]Alexandru C. Iordan, Magnus Jahre
Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. ICCS 2013: 1814-1823 - [c7]Alexandru C. Iordan, Magnus Jahre
On the energy footprint of task based parallel applications. HPCS 2013: 164-171 - 2011
- [j3]Marius Grannæs, Magnus Jahre, Lasse Natvig:
Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. J. Instr. Level Parallelism 13 (2011) - [j2]Magnus Jahre
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 1-20 (2011) - [c6]Marius Grannæs, Magnus Jahre
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. ARCS 2011: 135-146 - 2010
- [c5]Marius Grannæs, Magnus Jahre
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. HiPEAC 2010: 247-261 - [c4]Magnus Jahre
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. HiPEAC 2010: 292-306 - [i1]Magnus Jahre, Lasse Natvig:
Computational Computer Architecture Research at NTNU. ERCIM News 2010(81) (2010)
2000 – 2009
- 2009
- [j1]Guttorm Sindre
Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Trans. Educ. 52(1): 10-18 (2009) - [c3]Magnus Jahre
A light-weight fairness mechanism for chip multiprocessor memory systems. Conf. Computing Frontiers 2009: 1-10 - [c2]Magnus Jahre
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. HPCC 2009: 622-629 - 2008
- [c1]Marius Grannæs, Magnus Jahre
Low-cost open-page prefetch scheduling in chip multiprocessors. ICCD 2008: 390-396
Coauthor Index
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last updated on 2024-10-07 22:14 CEST by the dblp team
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