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17. ACM Great Lakes Symposium on VLSI 2007: Stresa, Lago Maggiore, Italy
- Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud:
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. ACM 2007, ISBN 978-1-59593-605-9 - Philippe Magarshack:
Design challenges in 45nm and below: DFM, low-power and design for reliability. 1
Architecture and memory
- Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. 2-7 - Chunyue Liu, Xiaolang Yan, Xing Qin:
An optimized linear skewing interleave scheme for on-chip multi-access memory systems. 8-13 - Sangyeun Cho:
I-cache multi-banking and vertical interleaving. 14-19 - Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto:
A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc. 20-24
Timing and power analysis
- Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack:
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. 25-30 - Yanming Jia, Yici Cai, Xianlong Hong:
Dummy fill aware buffer insertion during routing. 31-36 - Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas:
Probabilistic gate-level power estimation using a novel waveform set method. 37-42 - Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints. 43-48
Test and reliability
- Bin Zhou, Yizheng Ye, Yongsheng Wang:
Simultaneous reduction in test data volume and test time for TRC-reseeding. 49-54 - Cristiana Bolchini
, Davide Quarta, Marco D. Santambrogio
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration. 55-60 - Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham:
Estimating path delay distribution considering coupling noise. 61-66 - Soheil Aminzadeh, Saeed Safari
Co-evolutionary high-level test synthesis. 67-72
Device, interconnect, and power optimization for nano-CMOS
- Tarun Sairam, Wei Zhao, Yu Cao:
Optimizing finfet technology for high-speed and low-power design. 73-77 - Jacopo Giorgetti, Giuseppe Scotti
Analysis of data dependence of leakage current in CMOS cryptographic hardware. 78-83 - Yan Zhang, Mircea R. Stan
Temperature-aware circuit design using adaptive body biasing. 84-89 - Ioannis Papaefstathiou
A buffered crossbar-based chip interconnection framework supporting quality of service. 90-95
Emerging technologies
- Daniel Große
Exact sat-based toffoli network synthesis. 96-101 - Tejaswi Gowda
Combinational equivalence checking for threshold logic circuits. 102-107 - Nadine Gergel-Hackett, Garrett S. Rose
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. 108-113 - Juan Núñez
Operation limits in RTD-based ternary quantizers. 114-119
Low power architecture and interconnect
- Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson
Transition-activity aware design of reduction-stages for parallel multipliers. 120-125 - Chun-Mok Chung, Jihong Kim, Dohyung Kim:
Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts. 126-131 - Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley
GALS SoC interconnect bus for wireless sensor network processor platforms. 132-137 - Andrew Robinson, Jim D. Garside
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. 138-143
Poster session 1
- Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede
Side-channel resistant system-level design flow for public-key cryptography. 144-147 - R. G. Raghavendra, Bharadwaj Amrutur:
Area efficient loop filter design for charge pump phase locked loop. 148-151 - Dariusz Kania
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. 152-155 - Dan Li, Tingcun Wei, Wei Wu:
A novel charge recycler for TFT-LCD source driver IC. 156-159 - Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga:
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. 160-163 - Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis:
Compiler assisted architectural exploration for coarse grained reconfigurable arrays. 164-167 - Linga Reddy Cenkeramaddi
Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging. 168-171 - Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi:
RT level reliability enhancement by constructing dynamic TMRS. 172-175 - Atabak Mahram, Mehrdad Najibi, Hossein Pedram:
An asynchronous fpga logic cell implementation. 176-179 - Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera
Real-time implementation of a time-frequency analysis scheme. 180-183 - Maurizio Martina, Guido Masera
Flexible blocks for high throughput serially concatenated convolutional codes. 184-187 - Sreehari Veeramachaneni
Novel architectures for efficient (m, n) parallel counters. 188-191 - Mustafa Altun
High CMRR current mode operational amplifier with a novel class AB input stage. 192-195 - Barbara Cerato, Guido Masera
Hardware architecture for matrix factorization in mimo receivers. 196-199 - C. Hess, Markus Wenk, Andreas Burg
Reduced-complexity mimo detector with close-to ml error rate performance. 200-203 - Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. 204-207 - Drew C. Ness, Christian J. Hescott, David J. Lilja:
Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic. 208-211 - Osman Musa Abdulkarim, Maitham Shams:
A symmetric mos current-mode logic universal gate for high speed applications. 212-215 - Brandon L. Dell, Jonathan F. Bolus, Travis N. Blalock:
An automated unique tagging system using CMOS process variation. 216-218 - Antonino Tumeo
A design kit for a fully working shared memory multiprocessor on FPGA. 219-222 - Karthikeyan Lingasubramanian, Sanjukta Bhanja:
Probabilistic maximum error modeling for unreliable logic circuits. 223-226 - Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski:
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology. 227-230 - Kimish Patel, Wonbok Lee, Massoud Pedram:
Active bank switching for temperature control of the register file in a microprocessor. 231-234 - Chanseok Hwang, Peng Rong, Massoud Pedram:
Sleep transistor distribution in row-based MTCMOS designs. 235-240
Circuits and logic
- Luca Sterpone
A new decompression system for the configuration process of SRAM-based FPGAS. 241-246 - Kambiz Rahimi:
Minimizing peak power in synchronous logic circuits. 247-252 - Cosmin Popa:
Linearized CMOS active resistor independent on the bulk effect. 253-256 - Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
Structured and tuned array generation (STAG) for high-performance random logic. 257-262
Emerging technologies for low power design
- Frank Sill
Design of mixed gates for leakage reduction. 263-268 - Paulo F. Butzen
Modeling and estimating leakage current in series-parallel CMOS networks. 269-274 - Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun:
Analyzing and modeling process balance for sub-threshold circuit design. 275-280 - Chih-Nan Wu, Wei-Chung Cheng:
Viewing direction-aware backlight scaling. 281-286
Digital synthesis
- Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers:
Synthesis of irregular combinational functions with large don't care sets. 287-292 - Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar
DAG based library-free technology mapping. 293-298 - Mehrdad Najibi, Kamran Saleh, Hossein Pedram:
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. 299-304 - Andrea Ricci
An evolutionary approach for standard-cell library reduction. 305-310 - Salvatore Carta, Andrea Acquaviva, Pablo García Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. 311-316 - Sachin S. Sapatnekar
Computer-aided design of 3d integrated circuits. 317
Embedded tutorial
- Jamil Kawa, Charles C. Chiang:
DFM issues for 65nm and beyond. 318-322
ASIP/ASIC
- Hai Lin, Yunsi Fei
Utilizing custom registers in application-specific instruction set processors for register spills elimination. 323-328 - Naser MohammadZadeh
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. 329-334 - Alberto Dassatti
Beyond 3G wireless communication system prototype. 335-340 - Luca Sterpone
A new hardware architecture for performing the gridding of DNA microarray images. 341-346
System level design
- Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A design methodology for space-time adapter. 347-352 - Tarvo Raudvere, Ingo Sander
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. 353-358 - Amin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari
HW/SW partitioning using discrete particle swarm. 359-364 - Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. 365-370
CMOS & logic applications optimization and techniques
- Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. 371-376 - Roghoyeh Salmeh, Brent Maundy:
A 5 GHz wide band input and output matched low noise amplifier. 377-380 - Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf:
A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission. 381-386 - Paolo Bernardi
Design of an UHF RFID transponder for secure authentication. 387-392
Verification techniques
- Fei He, Xiaoyu Song, Ming Gu, Jiaguang Sun:
Effective heuristics for counterexample-guided abstraction refinement. 393-398 - Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham:
Reducing verification overhead with RTL slicing. 399-404 - Ralf Wimmer
Optimization techniques for BDD-based bisimulation computation. 405-410 - Paolo Bernardi
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. 411-416
Optimization and verification
- Anna Bernasconi
An approximation algorithm for fully testable kEP-SOP networks. 417-422 - Muharrem Orkun Saglamdemir, Ömer Yetik, Selçuk Talay, Günhan Dündar
A coefficient optimization and architecture selection tool for SD modulators considering component non-idealities. 423-428 - Chandan Karfa
Hand-in-hand verification of high-level synthesis. 429-434 - Taeko Matsunaga, Yusuke Matsunaga:
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. 435-440
Poster session 2
- Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
A new algorithm for the largest compositionally progressive solution of synchronous language equations. 441-444 - Giovanni Agosta
An efficient cost-based canonical form for Boolean matching. 445-448 - Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson:
Evaluation of using active circuitry for substrate noise suppression. 449-452 - Hamid Noori
The effect of temperature on cache size tuning for low energy embedded systems. 453-456 - Samuel Evain, Jean-Philippe Diguet:
Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. 457-460 - Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu:
Skew spreading for peak current reduction. 461-464 - Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh:
Block placement to ensure channel routability. 465-468 - Manuel F. M. Barros
GA-SVM feasibility model and optimization kernel applied to analog IC design automation. 469-472 - Xinjie Wei, Yici Cai, Xianlong Hong:
Physical aware clock skew rescheduling. 473-476 - Rachit Kumar Gupta, Vikas Narang, H. M. Roopashree, Vinod Menezes:
A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots. 477-480 - Koji Ohashi, Mineo Kaneko:
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. 481-484 - Raffaella Gentilini, Klaus Schneider
Three-valued automated reasoning on analog properties. 485-488 - Olga Golubeva, Mirko Loghi, Massimo Poncino:
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. 489-492 - Daniel Große
Improvements for constraint solving in the systemc verification library. 493-496 - Hamed Aminzadeh, Mohammad Danaie
Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints. 497-500 - Andrea Calimera
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. 501-504 - Marcello Mura, Marco Paolieri, Luca Negri, Mariagiovanna Sami:
StateCharts to systemc: a high level hardware simulation approach. 505-508 - Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini
A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip. 509-512 - Shiho Hagiwara
Improvement of power distribution network using correlation-based regression analysis. 513-516 - Deniz Dal
A high-level register optimization technique for minimizing leakage and dynamic power. 517-520 - Hamid Reza Kheirabadi, Morteza Saheb Zamani
An efficient net ordering algorithm for buffer insertion. 521-524 - Jia Wang, Ming-Yang Kao, Hai Zhou:
Address generation for nanowire decoders. 525-528 - Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. 529-533
Arithmetic and coding
- Nele Mentens
Efficient pipelining for modular multiplication architectures in prime fields. 534-539 - Chichyang Chen, Paul Chow:
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. 540-545 - Dong-Ho Lee, Jong-Soo Oh:
Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography. 546-551
Routing and buffer insertion
- Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat
Floorplan repair using dynamic whitespace management. 552-557 - Ali Jahanian
Improved timing closure by early buffer planning in floor-placement design flow. 558-563 - Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. 564-569 - Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis. 570-575
Power estimation and modeling
- Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang:
RT-level vector selection for realistic peak power simulation. 576-581 - Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
A fast clock scheduling for peak power reduction in LSI. 582-587 - Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay:
A path based modeling approach for dynamic power estimation. 588-593 - Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung:
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. 594-599 - Georges G. E. Gielen:
Future trends for wireless communication frontends in nanometer CMOS. 600-605
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