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Chun-Lung Hsu
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2020 – today
- 2024
- [c24]Chun-Lung Hsu, Hsuan-Yu Chen, Yi-Lin Chen:
Special Session: Architecture-Level DCIM Technologies for Edge AI Computing Applications. DFT 2024: 1-6 - 2021
- [j20]Tommy Sugiarto
, Chun-Lung Hsu, Chi-Tien Sun
Surface EMG vs. High-Density EMG: Tradeoff Between Performance and Usability for Head Orientation Prediction in VR Application. IEEE Access 9: 45418-45427 (2021) - [j19]Shyue-Kung Lu
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J. Electron. Test. 37(4): 503-513 (2021) - [c23]Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS 2021: 1-2 - [c22]Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC 2021: 208-212 - 2020
- [j18]Shyue-Kung Lu
Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 634-645 (2020) - [c21]Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun:
Testing of Configurable 8T SRAMs for In-Memory Computing. ATS 2020: 1-5 - [c20]Shi-Rou Lin, Wei-Hung Lin, Shih-Hsu Huang, Chun-Lung Hsu, Chi-Tien Sun:
Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. ICCE-TW 2020: 1-2 - [c19]Tommy Sugiarto
Head-Orientation-Prediction Based on Deep Learning on sEMG for Low-Latency Virtual Reality Application. IRC 2020: 183-186 - [c18]Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun:
ECC Caching Techniques for Protecting NAND Flash Memories. ITC-Asia 2020: 47-52 - [c17]Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun:
Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [j17]Shyue-Kung Lu
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. J. Electron. Test. 35(4): 485-495 (2019) - [c16]Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang:
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC 2019: 1-3 - [c15]Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Testing stuck-open faults of priority address encoder in content addressable memories. ASP-DAC 2019: 347-351 - [c14]Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Testing of In-Memory-Computing 8T SRAMs. DFT 2019: 1-4 - 2018
- [j16]Wei-Chun Hsu, Tommy Sugiarto
Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders. Sensors 18(10): 3397 (2018) - [c13]Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Diagnosis of Resistive Nonvolatile-8T SRAMs. ISOCC 2018: 23-24 - 2016
- [j15]Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen:
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. J. Electron. Test. 32(2): 111-123 (2016) - 2015
- [c12]Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu:
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC 2015: 520-525 - 2013
- [c11]Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. Asian Test Symposium 2013: 107-108 - [c10]Bing-Chuan Bai
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium 2013: 123-127 - 2012
- [j14]Chun-Lung Hsu, Yu-Sheng Huang, Fong-Chao Lee:
Interlaced switch boxes placement for three-dimensional FPGA architecture design. Int. J. Circuit Theory Appl. 40(5): 489-502 (2012) - [j13]Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu:
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 665-672 (2012) - 2011
- [j12]Chun-Lung Hsu, Yu-Sheng Huang, Ming-Da Chang, Hung-Yen Huang:
Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder. IEEE Trans. Computers 60(5): 628-638 (2011) - [c9]Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin:
High reliability built-in self-detection and self-correction design for DCT/IDCT application. SoCC 2011: 213-218 - 2010
- [j11]Chun-Lung Hsu, Chang-Hsin Cheng, Yu Liu:
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 319-324 (2010) - [c8]Hung-Yen Huang, Yu-Sheng Huang, Chun-Lung Hsu:
Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits. APCCAS 2010: 56-59 - [c7]Chun-Lung Hsu, Ching-Fen Wu:
High-performance 3D-SRAM architecture design. APCCAS 2010: 907-910 - [c6]Min-Ju Chan, Chun-Lung Hsu:
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip. DFT 2010: 122-128 - [c5]Chun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang:
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications. DFT 2010: 136-143
2000 – 2009
- 2009
- [j10]Chun-Lung Hsu, Yi-Ting Lai:
Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application. IEEE Trans. Instrum. Meas. 58(6): 1897-1906 (2009) - [j9]Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin:
Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits. IEEE Trans. Instrum. Meas. 58(7): 2196-2208 (2009) - [j8]Chun-Lung Hsu, Ting-Hsuan Chen:
Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA. IEEE Trans. Instrum. Meas. 58(7): 2300-2315 (2009) - 2008
- [j7]Chun-Lung Hsu, Yu-Sheng Huang:
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. J. Signal Process. Syst. 52(3): 211-229 (2008) - [c4]Yu-Sheng Huang, Chen-Kai Chen, Chun-Lung Hsu:
Efficient built-in self-test for video coding cores: A case study on motion estimation computing array. APCCAS 2008: 1751-1754 - 2007
- [j6]Chun-Lung Hsu, Mean-Hom Ho:
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2818-2825 (2007) - 2006
- [j5]Chun-Lung Hsu, Mean-Hom Ho, Chin-Feng Lin:
New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 377-384 (2006) - [c3]Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen:
An Adaptive Low-Power Control Scheme for On-Chip Network Applications. APCCAS 2006: 113-118 - [c2]Chun-Lung Hsu, Mean-Hom Ho, Yu-Kuan Wu, Ting-Hsuan Chen:
Design of Low-Frequency Low-Pass Filters for Biomedical Applications. APCCAS 2006: 690-695 - [c1]Chun-Lung Hsu, Yu-Kuan Wu, Yi-Ting Lai, Mean-Hom Ho:
Design of current-mode resonator for wireless applications. ISCAS 2006 - 2005
- [j4]Chun-Lung Hsu, Wen-Tso Wang, Ying-Fu Hong:
Frequency-Scaling Approach for Managing Power Consumption in NOCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3580-3583 (2005) - [j3]Chun-Lung Hsu, Yi-Ting Lai, Shu-Wei Wang:
Built-in self-test for phase-locked loops. IEEE Trans. Instrum. Meas. 54(3): 996-1002 (2005) - 2004
- [j2]Chun-Lung Hsu:
Control and Observation Structure for Analog Circuits with Current Test Data. J. Electron. Test. 20(1): 39-44 (2004) - 2003
- [j1]Chun-Lung Hsu, Wu-Hung Lu:
Design of High-Performance Charge-Pump Circuit for PLL Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3211-3213 (2003)
Coauthor Index
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