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Nitin Chandrachoodan
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2020 – today
- 2024
- [i5]Swathi Shree Narashiman, Nitin Chandrachoodan:
AlphaZip: Neural Network-Enhanced Lossless Text Compression. CoRR abs/2409.15046 (2024) - 2023
- [j17]Dara Nagaraju
, Nitin Chandrachoodan:
Compressing fully connected layers of deep neural networks using permuted features. IET Comput. Digit. Tech. 17(3-4): 149-161 (2023) - [j16]Dara Nagaraju
Slimmer CNNs Through Feature Approximation and Kernel Size Reduction. IEEE Open J. Circuits Syst. 4: 188-202 (2023) - [j15]Gargi Mitra
Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. IEEE Trans. Dependable Secur. Comput. 20(5): 3734-3752 (2023) - [c37]Dara Nagaraju
Work-in-Progress: QRCNN: Scalable CNNs. CASES 2023: 5-6 - [c36]Shashank Nag, Gourav Datta, Souvik Kundu, Nitin Chandrachoodan, Peter A. Beerel
ViTA: A Vision Transformer Inference Accelerator for Edge Applications. ISCAS 2023: 1-5 - [i4]Shashank Nag, Gourav Datta, Souvik Kundu, Nitin Chandrachoodan, Peter A. Beerel:
ViTA: A Vision Transformer Inference Accelerator for Edge Applications. CoRR abs/2302.09108 (2023) - 2022
- [j14]Pani Prithvi Raj
Reduced Memory Viterbi Decoding for Hardware-accelerated Speech Recognition. ACM Trans. Embed. Comput. Syst. 21(3): 31:1-31:18 (2022) - [c35]Arjun Menon Vadakkeveedu, Debabrata Mandal, Pradeep Ramachandran, Nitin Chandrachoodan:
Split-Knit Convolution: Enabling Dense Evaluation of Transpose and Dilated Convolutions on GPUs. HIPC 2022: 1-10 - [c34]Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan:
Layerwise Disaggregated Evaluation of Spiking Neural Networks. ISLPED 2022: 25:1-25:6 - [i3]Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti:
Snoopy: A Webpage Fingerprinting Framework with Finite Query Model for Mass-Surveillance. CoRR abs/2205.15037 (2022) - 2021
- [j13]Celia Dharmaraj
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. IET Comput. Digit. Tech. 15(2): 97-111 (2021) - [j12]Basava Naga Girish Koneru
A Smoothed LASSO-Based DNN Sparsification Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4287-4298 (2021) - [j11]Celia Dharmaraj
Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders. ACM Trans. Embed. Comput. Syst. 20(2): 12:1-12:25 (2021) - 2020
- [j10]Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. IET Comput. Digit. Tech. 14(3): 122-131 (2020) - [c33]Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan:
Depending on HTTP/2 for Privacy? Good Luck! DSN 2020: 278-285 - [c32]Sathish Panchapakesan, Zhenman Fang, Nitin Chandrachoodan:
EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA. FCCM 2020: 242 - [c31]Sundarrajan Rangachari, Nitin Chandrachoodan:
Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths. ISCAS 2020: 1-5 - [i2]Abinand Nallathambi, Nitin Chandrachoodan:
Probabilistic spike propagation for FPGA implementation of spiking neural networks. CoRR abs/2001.09725 (2020)
2010 – 2019
- 2019
- [j9]Shivani Bathla
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 376-386 (2019) - [c30]Younghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan
Data Subsetting: A Data-Centric Approach to Approximate Computing. DATE 2019: 576-581 - [c29]Gargi Mitra, Prasanna Karthik Vairam
White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. SIGCOMM Posters and Demos 2019: 122-124 - [i1]Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan:
White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. CoRR abs/1903.06475 (2019) - 2018
- [c28]D. Celia, Vinita Vasudevan
Optimizing power-accuracy trade-off in approximate adders. DATE 2018: 1488-1491 - [c27]Karthikeyan Natarajan, Nitin Chandrachoodan
Lossless Parallel Implementation of a Turbo Decoder on GPU. HiPC 2018: 133-142 - [c26]D. Celia, Vinita Vasudevan
Probabilistic Error Modeling for Two-part Segmented Approximate Adders. ISCAS 2018: 1-5 - 2017
- [j8]Sundarrajan Rangachari
Scenario-Aware Dynamic Power Reduction Using Bias Addition. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 450-461 (2017) - [c25]Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. DFT 2017: 1-4 - [c24]Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan:
FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only). FPGA 2017: 295 - 2016
- [c23]D. Celia, Nitin Chandrachoodan
Guided multilevel approximation of less significant bits for power reduction. VDAT 2016: 1-6 - [c22]Amit Salaskar, Nitin Chandrachoodan
FFT/IFFT implementation using Vivado™ HLS. VDAT 2016: 1-2 - 2015
- [j7]Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. 21(1): 14:1-14:25 (2015) - [c21]Chaitanya Peddawad, Aman Goel
iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal. ICCAD 2015: 903-909 - [c20]Karthikeyan Natarajan, Nitin Chandrachoodan
Non-uniform DFT implementation for channel simulations in GPU. NCC 2015: 1-6 - [c19]Vaibhav Pratap Singh, Nitin Chandrachoodan
Designing a passive star optical network for the India-based Neutrino Observatory. NCC 2015: 1-6 - 2014
- [c18]Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan
Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability. VLSID 2014: 359-364 - 2013
- [c17]Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. DAC 2013: 182:1-182:7 - [c16]Shuo Qiao, Anil Prabhakar
An inertial sensor-based system to develop motor capacity in children with cerebral palsy. EMBC 2013: 6111-6114 - [c15]Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. ETS 2013: 1 - [c14]Sundarrajan Rangachari, Nitin Chandrachoodan
Scalable low power digital filter architectures for varying input dynamic range. ISCAS 2013: 3018-3021 - [c13]Prabhat Avasare, Nitin Chandrachoodan
Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon. VLSI Design 2013 - 2012
- [j6]Seetal Potluri, Nitin Chandrachoodan
Interconnect Aware Test Power Reduction. J. Low Power Electron. 8(4): 516-525 (2012) - [j5]Manish Kumar Jaiswal, Nitin Chandrachoodan
FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers 61(1): 60-72 (2012) - [c12]Bharath Kumar Reddy L., Nitin Chandrachoodan
A GPU implementation of belief propagation decoder for polar codes. ACSCC 2012: 1272-1276 - [c11]Dhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan
GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications. VLSI Design 2012: 149-154 - 2011
- [j4]Nitin Chandrachoodan
24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electron. 7(4): 459 (2011) - [c10]Seetal Potluri, Nitin Chandrachoodan
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI 2011: 319-320
2000 – 2009
- 2009
- [c9]Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design 2009: 267-271 - 2008
- [c8]Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. ICIIS 2008: 1-4 - [c7]Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design 2008: 169-174 - 2007
- [c6]Karthick Parashar, Nitin Chandrachoodan
A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. FPL 2007: 792-795 - [c5]Kannan Gaddam, Nitin Chandrachoodan
Rapid Abstract Control Model for Signal Processing Implementation. SiPS 2007: 418-423 - 2004
- [j3]Nitin Chandrachoodan
The hierarchical timing pair model for multirate DSP applications. IEEE Trans. Signal Process. 52(5): 1209-1217 (2004) - 2003
- [j2]Arun Raghupathy, Nitin Chandrachoodan, K. J. Ray Liu:
Algorithm and VLSI architecture for high performance adaptive video scaling. IEEE Trans. Multim. 5(4): 489-502 (2003) - 2002
- [j1]Nitin Chandrachoodan
High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection. EURASIP J. Adv. Signal Process. 2002(9): 893-907 (2002) - 2001
- [c4]Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu:
An efficient timing model for hardware implementation of multirate dataflow graphs. ICASSP 2001: 1153-1156 - [c3]Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu:
Adaptive negative cycle detection in dynamic graphs. ISCAS (5) 2001: 163-166 - [c2]Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu:
The hierarchical timing pair model. ISCAS (5) 2001: 367-370
1990 – 1999
- 1999
- [c1]Arun Raghupathy, Pohsiang Hsu, K. J. Ray Liu, Nitin Chandrachoodan:
VLSI architecture and design for high performance adaptive video scaling. ISCAS (4) 1999: 406-409
Coauthor Index
aka: Kamakoti Veezhinathan
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