default search action
ACM Transactions on Design Automation of Electronic Systems, Volume 21
Volume 21, Number 1, November 2015
- Debashri Roy, Prasun Ghosal, Saraju P. Mohanty:
FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits. 1:1-1:38 - Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. 2:1-2:25 - Hu Chen, Sanghamitra Roy
, Koushik Chakraborty:
DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors. 3:1-3:21 - Myungsun Kim, Jinkyu Koo, Hyojung Lee, James R. Geraci:
Memory Management Scheme to Improve Utilization Efficiency and Provide Fast Contiguous Allocation without a Statically Reserved Area. 4:1-4:23 - Fabian Oboril, Mehdi Baradaran Tahoori:
Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design. 5:1-5:26 - Ankit More, Baris Taskin:
Locality-Aware Network Utilization Balancing in NoCs. 6:1-6:26 - Hsiang-Yun Cheng
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. 7:1-7:26 - Gilberto Ochoa-Ruiz
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems. 8:1-8:25 - Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Leakage Power. 9:1-9:33 - Anupama R. Subramaniam, Janet Roveda, Yu Cao
A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching. 10:1-10:25 - Dongha Jung, Hokyoon Lee, Seon Wook Kim:
Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy. 11:1-11:24 - Ying Qin, ShengYu Shen, Qingbo Wu, Huadong Dai, Yan Jia:
Complementary Synthesis for Encoder with Flow Control Mechanism. 12:1-12:26 - Irith Pomeranz:
Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation. 13:1-13:20 - Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. 14:1-14:25 - Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo:
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs. 15:1-15:17 - Jin Sun, Claudio Talarico, Priyank Gupta, Janet Roveda:
A New Uncertainty Budgeting-Based Method for Robust Analog/Mixed-Signal Design. 16:1-16:25 - Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman
Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips. 17:1-17:33 - Chung-Wei Lin, Bowen Zheng, Qi Zhu
Security-Aware Design Methodology and Optimization for Automotive Systems. 18:1-18:26
Volume 21, Number 2, January 2016
- Daming Zhang, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications. 19:1-19:32 - Laurence Pierre:
Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements. 20:1-20:29 - Jin-Tai Yan
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs. 21:1-21:24 - Angeliki Kritikakou
Array Size Computation under Uniform Overlapping and Irregular Accesses. 22:1-22:35 - Youngsik Kim, Sungjoo Yoo, Sunggu Lee:
Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM. 23:1-23:27 - Dong Xiang, Kele Shen:
A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing. 24:1-24:23 - Zipeng Li, Tsung-Yi Ho
Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction. 25:1-25:27 - Le Zhang, Vivek Sarin:
Parallel Power Grid Analysis Based on Enlarged Partitions. 26:1-26:21 - Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. 27:1-27:14 - Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions. 28:1-28:25 - Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, Yuan Xie:
TSocket: Thermal Sustainable Power Budgeting. 29:1-29:22 - Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Reliability-Aware Resource Allocation and Binding in High-Level Synthesis. 30:1-30:27 - Jeremy Dubeuf, David Hély
ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes. 31:1-31:24 - Martin Lukasiewycz, Philipp Mundhenk, Sebastian Steinhorst
Security-Aware Obfuscated Priority Assignment for Automotive CAN Platforms. 32:1-32:27 - Chandra K. H. Suresh, Ozgur Sinanoglu
Adapting to Varying Distribution of Unknown Response Bits. 33:1-33:22 - Jingweijia Tan, Zhi Li, Mingsong Chen, Xin Fu:
Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory. 34:1-34:25 - Irith Pomeranz:
Design-for-Testability for Functional Broadside Tests under Primary Input Constraints. 35:1-35:18
Volume 21, Number 3, July 2016
- Evangeline F. Y. Young, Azadeh Davoodi:
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. 36:1 - Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick
Eh?Placer: A High-Performance Modern Technology-Driven Placer. 37:1-37:27 - Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos
Clock-Tree-Aware Incremental Timing-Driven Placement. 38:1-38:27 - Po-Hsun Wu, Mark Po-Hung Lin
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching. 39:1-39:22 - Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin:
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect. 40:1-40:23 - Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, Iris Hui-Ru Jiang:
Analytical Clustering Score with Application to Postplacement Register Clustering. 41:1-41:18 - Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. 42:1-42:21 - Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan:
EBL Overlapping Aware Stencil Planning for MCC System. 43:1-43:24 - Seungwon Kim, Seokhyeong Kang, Ki Jin Han
Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC. 44:1-44:19 - Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang:
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. 45:1-45:21
- Chao Wang, Chuansheng Dong, Haibo Zeng, Zonghua Gu
Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling. 46:1-46:25 - Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, Sunggu Lee:
Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study. 47:1-47:25 - Xing Huang, Wenzhong Guo, Genggeng Liu
FH-OAOS: A Fast Four-Step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction. 48:1-48:31 - Sparsh Mittal
A Survey of Techniques for Cache Locking. 49:1-49:24 - Ramachandran Venkatasubramanian, Robert Elio, Sule Ozev:
Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp. 50:1-50:19 - Sangmin Kim, Seokhyeong Kang, Youngsoo Shin:
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. 51:1-51:23 - Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. 52:1-52:38 - Hany Kashif, Hiren D. Patel, Sebastian Fischmeister:
Path Selection for Real-Time Communication on Priority-Aware NoCs. 53:1-53:25 - Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young:
An Effective Chemical Mechanical Polishing Fill Insertion Approach. 54:1-54:21
Volume 21, Number 4, September 2016
- Marcela Zuluaga, Peter A. Milder
Streaming Sorting Networks. 55:1-55:30 - Yue Zhao, Taeyoung Kim
Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection. 56:1-56:21 - Rickard Ewetz, Cheng-Kok Koh:
Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression. 57:1-57:27 - Hassan Ghasemzadeh, Ramin Fallahzadeh, Roozbeh Jafari
A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition Using Wearables. 58:1-58:27 - Adam Teman
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. 59:1-59:25 - Swaminathan Narayanaswamy, Steffen Schlüter, Sebastian Steinhorst
On Battery Recovery Effect in Wireless Sensor Nodes. 60:1-60:28 - Dani A. Tannir, Ya Wang, Peng Li:
Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques. 61:1-61:15 - Sebastian Steinhorst
Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs. 62:1-62:26 - Ujjwal Guin, Qihang Shi, Domenic Forte
FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs. 63:1-63:20 - William Lee, Vikas S. Vij, Kenneth S. Stevens:
Timing Path-Driven Cycle Cutting for Sequential Controllers. 64:1-64:25 - Yang Xu, Jürgen Teich:
Hierarchical Statistical Leakage Analysis and Its Application. 65:1-65:22 - Ramprasath S
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. 66:1-66:27 - Hongfei Wang, R. D. (Shawn) Blanton:
Ensemble Reduction via Logic Minimization. 67:1-67:17 - Irith Pomeranz:
N-Detection Test Sets for Circuits with Multiple Independent Scan Chains. 68:1-68:15 - Jae-Yeon Won, Paul V. Gratz
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. 69:1-69:25 - Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta
Area-Aware Decomposition for Single-Electron Transistor Arrays. 70:1-70:20 - Fubing Mao, Yi-Chung Chen, Wei Zhang
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration. 71:1-71:26 - Anna Bernasconi, Valentina Ciriani:
Index-Resilient Zero-Suppressed BDDs: Definition and Operations. 72:1-72:27
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-23 19:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: