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14th Asian Test Symposium 2005: Calcutta, India
- 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India. IEEE Computer Society 2005, ISBN 0-7695-2481-8
Cover
- Title Page.
- Copyright.
Introduction
- Foreword.
- ATS Steering Committee.
- Advisory Board and Organizing Committee.
- Program Committee.
- Reviewers.
- Best Paper Awards (2002 and 2003).
- TTTC Introduction.
- TTEP Introduction.
Tutorials
- Yervant Zorian, Juan Antonio Carballo:
T1: Design for Manufacturability. - Adit D. Singh:
T2: Statistical Methods for VLSI Test and Burn-in Optimization.
Plenary Talk
- Thomas W. Williams:
Design for Testability: The Path to Deep Submicron.
Banquet Speeches
- Sanjiv Taneja:
DFT Aware Layout - Layout Aware DFT. - Janusz Rajski:
Embedded Test Technology - Brief History, Current Status, and Future Directions.
Invited Talks
- John P. Hayes:
Faults and Tests in Quantum Circuits. - Sreejit Chakravarty:
Improving Logic Test Quality of Microprocessors.
Session A1: Analog and RF Testing: I
- Donghoon Han, Abhijit Chatterjee:
Robust Built-In Test of RF ICs Using Envelope Detectors. 2-7 - Haihua Yan, Adit D. Singh, Gefu Xu:
Delay Defect Characterization Using Low Voltage Test. 8-13 - Shalabh Goyal, Michael Purtell:
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester. 14-17 - Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka:
IDDQ Testing Method using a Scan Pattern for Production Testing. 18-21 - Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. 22-27
Session B1: Verification, On-line and Software Testing
- Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. 28-33 - Amir Hekmatpour, Azadeh Salehi:
Block-based Schema-driven Assertion Generation for Functional Verification. 34-39 - K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil:
A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. 40-45 - Guangmei Zhang, Chen Rui, Xiaowei Li, Congying Han:
The Automatic Generation of Basis Set of Path for Path Testing. 46-51
Session A2: Analog and RF Testing: II
- Yongsheng Wang, Jinxiang Wang, Fengchang Lai, Yizheng Ye:
Optimal Schemes for ADC BIST Based on Histogram. 52-57 - A. M. Majid, David C. Keezer
, J. V. Karia:
A 5 Gbps Wafer-Level Tester. 58-63 - Achintya Halder, Abhijit Chatterjee:
Low-cost Production Test of BER for Wireless Receivers. 64-69 - Shaolei Quan, Qiang Qiang, Chin-Long Wey:
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. 70-75
Session B2: Self-Checking, On-line and Software Testing
- Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel:
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. 76-81 - Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong:
A State Machine for Detecting C/C++ Memory Faults. 82-87 - Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar:
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. 88-93 - Philip Samuel, Rajib Mall:
Boundary Value Testing based on UML Models. 94-99
Session A3: Interconnect Testing
- Jiun-Lang Huang:
Random Jitter Testing Using Low Tap-Count Delay Lines. 100-105 - Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu:
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. 106-111 - Wichian Sirisaengtaksin, Sandeep K. Gupta:
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. 112-119 - Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li:
Non-robust Test Generation for Crosstalk-Induced Delay Faults. 120-125
Session B3: BIST
- Dong Xiang, Ming-Jing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. 126-131 - Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. 132-137 - Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed:
Low Transition LFSR for BIST-Based Applications. 138-143 - Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang:
A BIST Scheme Based on Selecting State Generation of Folding Counters. 144-149
Session A4: SoC Testing
- Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara:
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. 150-155 - Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi:
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. 156-161 - Anders Larsson, Erik Larsson
SOC Test Scheduling with Test Set Sharing and Broadcasting. 162-169
Session B4: Yield Enhancement
- Animesh Datta, Swarup Bhunia
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. 170-175 - Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. 176-181 - Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu
Flash Memory Die Sort by a Sample Classification Method. 182-187 - Junichi Hirase, Tatsuya Furukawa:
Chip Identification using the Characteristic Dispersion of Transistor. 188-193
Session A5: Delay and Defect-Based Testing
- Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. 194-201 - Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. 202-207 - I-De Huang, Sandeep K. Gupta:
Selection of Paths for Delay Testing. 208-215 - Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy:
On Improving Defect Coverage of Stuck-at Fault Tests. 216-223
Session B5: Low Power Testing
- Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
A Scan Matrix Design for Low Power Scan-Based Test. 224-229 - Youbean Kim, Myung-Hoon Yang, Yong Lee, Sungho Kang:
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. 230-235 - Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. 236-241 - Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
Partial Gating Optimization for Power Reduction During Test Application. 242-247
Session A6: Diagnosis, Delay, and Defect-Based Testing
- Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Bridge Defect Diagnosis with Physical Information. 248-253 - Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. 254-259 - Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic. 260-265 - Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 266-271
Session B6: Test Generation and Fault Simulation
- Dong Hyun Baik, Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. 272-277 - Shahrzad Mirkhani, Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering. 278-283 - Sukanta Das, Hafizur Rahaman
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. 284-287 - Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability. 288-293 - Vishwani D. Agrawal, Alok S. Doshi:
Concurrent Test Generation. 294-299
Session A7: Design for Testability
- V. R. Devanathan:
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. 300-305 - Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. 306-311 - Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press:
Achieving High Test Quality with Reduced Pin Count Testing. 312-317 - Dong Xiang, Kaiwei Li, Hideo Fujiwara:
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. 318-323
Session B7: Test Compression and Compaction
- Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. 324-329 - Sameer Goel, Rubin A. Parekhji:
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. 330-336 - Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya:
Efficient Test Compaction for Pseudo-Random Testing. 337-342 - Yu-Hsuan Fu, Sying-Jyan Wang
Test Data Compression with Partial LFSR-Reseeding. 343-347
Session A8: Design for Testability: II
- Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
CryptoScan: A Secured Scan Chain Architecture. 348-353 - Shiyi Xu:
Pseudo-Parity Testing with Testable Design. 354-359 - Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen:
Finite State Machine Synthesis for At-Speed Oscillation Testability. 360-365 - Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa:
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. 366-371
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
- Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. 372-377 - Aiman H. El-Maleh
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. 378-385 - Youhua Shi
Low Power Test Compression Technique for Designs with Multiple Scan Chain. 386-389 - Zhigang Jiang, Sandeep K. Gupta:
Threshold testing: Covering bridging and other realistic faults. 390-397
Session A9: Design for Testability: III
- Biplab K. Sikdar
Synthesis of Testable Finite State Machine Through Decomposition. 398-403 - Swaroop Ghosh, Swarup Bhunia
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. 404-409 - Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay:
Flip-flop chaining architecture for power-efficient scan during test application. 410-413 - Varun Arora, Indranil Sengupta:
A Unified Approach to Partial Scan Design using Genetic Algorithm. 414-421
Session B9: Fault Modeling, Processor Testing, and Memory Testing
- Ilia Polian, Thomas Fiehn, Bernd Becker
A Family of Logical Fault Models for Reversible Circuits. 422-427 - Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil:
Compressing Functional Tests for Microprocessors. 428-433 - Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath:
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. 434-439 - Ji-Xue Xiao, Guang-Ju Chen, Yong-Le Xie:
Arithmetic Test Strategy for FFT Processor. 440-443 - Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. 444-449
Industry Session
Session C1: SoC Test Practices
- Tom Waayers, Erik Jan Marinissen
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. 450 - Rubin A. Parekhji:
DFT for Low Cost SOC Test. 451 - R. Chandramouli:
Managing Test and Repair of Embedded Memory Subsystem in SoC. 452
Session C2: Defect-Based Testing
- Prabhu Krishnamurthy:
The Ultimate Chase. 454 - Vikram Iyengar, Phil Nigh:
Defect-Oriented Test for Ultra-Low DPM. 455 - Hans A. R. Manhaeve:
Current Testing for Nanotechnologies: A Demystifying Application Perspective.. 456
Session C4: Advances in Test Generation and Verification
- Indradeep Ghosh
High Level Test Generation for Custom Hardware: An Industrial Perspective. 458 - Praveen Parvathala:
High Level Test Generation / SW based Embedded Test. 459 - Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu:
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. 460
Session C5: Test Data Compression and System Level Testing
- Kedarnath J. Balakrishnan:
Emerging Techniques for Test Data Compression. 462 - Nilanjan Mukherjee:
Improving Test Quality Using Test Data Compression. 463 - Tapan J. Chakraborty:
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. 464-465
Session C6: Mixed Signal Testing
- Sasikumar Cherubal:
Challenges in Next Generation Mixed-Signal IC Production Testing. 466 - Salem Abdennadher, Saghir A. Shaikh:
Practices in Testing of Mixed-Signal and RF SoCs. 467 - Salem Abdennadher, Saghir A. Shaikh:
Challenges in High Speed Interface Testing. 468
Session C7: Delay Testing and Burn-in Test Methodologies
- Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman:
Practical Aspects of Delay Testing for Nanometer Chips. 470 - T. M. Mak:
Limitation of structural scan delay test. 471 - Mohd Fairuz Zakaria, Zainal Abu Kassim, Melanie Po-Leen Ooi
Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST. 472
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