default search action
Chien-Nan Jimmy Liu
Chien-Nan Liu
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [c66]Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai:
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. MWSCAS 2024: 1085-1090 - [c65]Bo-Kai Kang, Hao-Ju Chang, Hung-Ming Chen, Chien-Nan Jimmy Liu:
ML/DL-Based Signal Integrity Optimization for InFO Routing. NewCAS 2024: 343-347 - [c64]Shih-Han Chang, Shih-Yu Chen, Chun-Wen Yang, Hau-Wei Huang, Yu-Cheng Yang, Wei-Liang Chen, Chien-Nan Liu, Hung-Ming Chen:
Mitigating Power and Process Variation for Analog CIM Design Migration. SMACD 2024: 1-4 - 2023
- [j34]Ling-Yen Song
, Chih-Yun Chou
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. ACM Trans. Design Autom. Electr. Syst. 28(2): 18:1-18:22 (2023) - [c63]Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC 2023: 352-357 - [c62]Hung-Ming Chen
Reshaping System Design in 3D Integration: Perspectives and Challenges. ISPD 2023: 71-77 - [c61]Po-Chun Wang, Mark Po-Hung Lin
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. SMACD 2023: 1-4 - 2022
- [c60]Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. ASP-DAC 2022: 80-85 - [c59]Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou:
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. DATE 2022: 208-213 - [c58]Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956 - [c57]Shih-Han Chang, Chien-Nan Jimmy Liu, Alexandra Küster:
Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing. SMACD 2022: 1-4 - [c56]Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD 2022: 1-4 - [c55]Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. VLSI-DAT 2022: 1-4 - 2021
- [j33]Hao-Yu Chi
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2556-2567 (2021) - [c54]Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou:
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. DATE 2021: 1218-1223 - [c53]Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC 2021: 262-263 - [c52]Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips. VLSI-DAT 2021: 1-4 - 2020
- [j32]Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Wire Load Oriented Analog Routing with Matching Constraints. ACM Trans. Design Autom. Electr. Syst. 25(6): 55:1-55:26 (2020) - [c51]Mark Po-Hung Lin
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8 - [c50]Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD 2020: 127:1-127:8
2010 – 2019
- 2019
- [c49]Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. ICCAD 2019: 1-6 - [c48]Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Structure-Based Methodology for Analog Layout Generation. SMACD 2019: 33-36 - 2018
- [c47]Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC 2018: 482-487 - [c46]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6 - [c45]Hsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh, Chien-Nan Jimmy Liu:
Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications. SMACD 2018: 169-172 - 2017
- [j31]Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu:
An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2370-2378 (2017) - [j30]Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu:
Cluster-based delta-QMC technique for fast yield analysis. Integr. 58: 64-73 (2017) - [c44]Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, Chien-Nan Jimmy Liu:
An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique. ATS 2017: 64-69 - [c43]Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao:
Non-regression approach for the behavioral model generator in mixed-signal system verification. VLSI-SoC 2017: 1-5 - [c42]Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia:
Layout placement optimization with isolation rings for high-voltage VLSI circuits. VLSI-DAT 2017: 1-4 - [c41]Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu:
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT 2017: 1-4 - 2016
- [c40]Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti
Wave digital filter based analog circuit emulation on FPGA. ISCAS 2016: 1286-1289 - 2015
- [c39]Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He:
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC 2015: 556-561 - [c38]Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He:
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA 2015: 276 - [c37]Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu:
Layout-aware analog synthesis environment with yield consideration. ISQED 2015: 589-593 - [c36]Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, Chien-Nan Jimmy Liu:
Low-noise analog synthesis platform for bio-signal acquisition system. VLSI-DAT 2015: 1-4 - 2014
- [j29]Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li:
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 24-35 (2014) - [c35]Hsing-Han Tseng, Shiou-Wen Wang, Jian-Yu Chen, Chien-Nan Jimmy Liu:
A novel design space reduction method for efficient simulation-based optimization. ISCAS 2014: 381-384 - [c34]Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu:
Simultaneous optimization for low dropout regulator and its error amplifier with process variation. VLSI-DAT 2014: 1-4 - 2013
- [j28]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. Integr. 46(3): 280-289 (2013) - [c33]Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu:
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. DATE 2013: 1458-1461 - [c32]Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen:
LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI 2013: 107-112 - [c31]Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu:
A layout-aware automatic sizing approach for retargeting analog integrated circuits. VLSI-DAT 2013: 1-4 - 2012
- [j27]Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu:
Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 845-857 (2012) - [j26]Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai:
A fast heuristic approach for parametric yield enhancement of analog designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 35:1-35:20 (2012) - [c30]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Improving design verifiability by early RTL coverability analysis. MEMOCODE 2012: 25-32 - [c29]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Reducing test point overhead with don't-cares. MWSCAS 2012: 534-537 - [c28]Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu:
Peak wake-up current estimation at gate-level with standard library information. VLSI-DAT 2012: 1-4 - 2011
- [j25]Chin-Lung Chuang, Chien-Nan Jimmy Liu:
Hybrid Testbench Acceleration for Reducing Communication Overhead. IEEE Des. Test Comput. 28(2): 40-51 (2011) - [j24]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. J. Inf. Sci. Eng. 27(1): 287-302 (2011) - [c27]Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu:
ILP-based inter-die routing for 3D ICs. ASP-DAC 2011: 330-335 - [c26]Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED 2011: 174-181 - 2010
- [j23]Mu-Shun Matt Lee, Chien-Nan Jimmy Liu:
Dynamic Supply Current Waveform Estimation with Standard Library Information. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(3): 595-606 (2010) - [j22]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(3): 664-668 (2010) - [j21]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Trans. Inf. Syst. 93-D(6): 1656-1660 (2010) - [j20]Chin-Cheng Kuo, Chien-Nan Jimmy Liu:
Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 44-52 (2010) - [c25]Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits. DAC 2010: 903-908 - [c24]Hsiu-Wen Li, Ren-Hong Fu, Hsin-Yu Luo, Chien-Nan Jimmy Liu:
Automatic circuit adjustment technique for process sensitivity reduction and yield improvement. ISCAS 2010: 2582-2585 - [c23]Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu, Chien-Nan Jimmy Liu:
Dynamic IR drop estimation at gate level with standard library information. ISCAS 2010: 2606-2609
2000 – 2009
- 2009
- [j19]Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo:
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. 92-C(7): 964-972 (2009) - [j18]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Trans. Commun. 92-B(11): 3557-3563 (2009) - [j17]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 272-284 (2009) - [j16]Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu:
A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 124-131 (2009) - [j15]Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, Ching-Ji Huang:
Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1160-1172 (2009) - [j14]Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu:
Design of an All-Digital LVDS Driver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1635-1644 (2009) - [c22]Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu:
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. ASP-DAC 2009: 516-521 - [c21]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. DATE 2009: 845-850 - 2008
- [j13]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24(1): 115-127 (2008) - [j12]Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu:
A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1026-1030 (2008) - [j11]Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su:
Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. IEEE Trans. Circuits Syst. Video Technol. 18(12): 1771-1775 (2008) - [j10]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13(4): 66:1-66:20 (2008) - [c20]Hungwen Lu, Chauchin Su, Chien-Nan Liu:
A scalable digitalized buffer for gigabit I/O. CICC 2008: 241-244 - [c19]Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin:
Quick supply current waveform estimation at gate level using existed cell library information. ACM Great Lakes Symposium on VLSI 2008: 135-138 - 2007
- [j9]Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu:
Hybrid Approach to Faster Functional Verification with Full Visibility. IEEE Des. Test Comput. 24(2): 154-162 (2007) - [j8]Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu:
An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 1038-1044 (2007) - [j7]Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou:
A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007) - [j6]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1509-1521 (2007) - [c18]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC 2007: 792-797 - [c17]Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu:
Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236 - 2006
- [j5]Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 391-398 (2006) - [j4]Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su:
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Trans. Electron. 89-C(11): 1713-1718 (2006) - [c16]Wei-Hsiang Cheng, Chin-Lung Chuang, Chien-Nan Jimmy Liu:
An efficient mechanism to provide full visibility for hardware debugging. ISCAS 2006 - [c15]Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu:
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. PATMOS 2006: 543-552 - [c14]Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu:
Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. SMC 2006: 960-965 - [c13]Chin-Cheng Kuo, Chien-Nan Jimmy Liu:
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. VLSI-SoC 2006: 116-121 - 2005
- [c12]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326 - [c11]Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ACM Great Lakes Symposium on VLSI 2005: 286-290 - [c10]Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu:
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. ISCAS (4) 2005: 3591-3594 - [c9]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) 2005: 5682-5685 - 2004
- [c8]Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu:
A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. Asian Test Symposium 2004: 164-169 - [c7]Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu:
On code coverage measurement for Verilog-A. HLDVT 2004: 115-120 - 2003
- [j3]Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou:
A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Des. Test Comput. 20(2): 48-55 (2003) - [j2]Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Power Model for IP-Level Complex Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 2073-2080 (2003) - [c6]Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An efficient IP-level power model for complex digital circuits. ASP-DAC 2003: 610-613 - 2002
- [c5]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367 - 2001
- [c4]Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou:
An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108 - [c3]Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377 - 2000
- [j1]Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Des. Test Comput. 17(3): 72-77 (2000) - [c2]Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan:
A novel approach for functional coverage measurement in HDL. ISCAS 2000: 217-220
1990 – 1999
- 1999
- [c1]Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-03 20:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: