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HLDVT 2004: Sonoma Valley, CA, USA
- Ninth IEEE International High-Level Design Validation and Test Workshop 2004, Sonoma Valley, CA, USA, November 10-12, 2004. IEEE Computer Society 2004, ISBN 0-7803-8714-7
Formal Techniques
- Chia-Chih Yen, Jing-Yang Jou:
Enhancing sequential depth computation with a branch-and-bound algorithm. 3-8 - William N. N. Hung, Naren Narasimhan:
Reference model based RTL verification: an integrated approach. 9-13 - Prakash Mohan Peranandam, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Dynamic guiding of bounded property checking. 15-18 - Ali Habibi, Sofiène Tahar:
Towards an efficient assertion based verification of SystemC designs. 19-22
Processor-Oriented Validation
- Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction level test methodology for CPU core software-based self-testing. 25-29 - Jason T. Higgins, Mark D. Aagaard:
Simplifying design and verification for structural hazards and datapaths in pipelined circuits. 31-36 - Ismet Bayraktaroglu, Manuel d'Abreu:
ATPG based functional test for data paths: application to a floating point unit. 37-40 - Miroslav N. Velev
:
Formal verification of pipelined processors with load-value prediction. 41-46
Decision Diagrams for Verification
- Tao Feng, Li-C. Wang
On using a 2-domain partitioned OBDD data structure in verification. 49-54 - Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon:
Variable ordering for taylor expansion diagrams. 55-59 - T. L. Rajaprabhu, Ashutosh Kumar Singh
MODD for CF: a representation for fast evaluation of multiple-output functions. 61-66
Validation Pattern Generation
- Franco Fummi, Cristina Marconcini, Graziano Pravadelli
Functional verification based on the EFSM model. 69-74 - Markus Braun, Shai Fine, Avi Ziv:
Enhancing the efficiency of Bayesian network based coverage directed test generation. 75-80 - Jorge Campos, Hussain Al-Asaad:
Mutation-based validation of high-level microprocessor implementations. 81-86
Behavioral Modeling
- Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
Effects of property ordering in an incremental formal modeling methodology. 89-94 - Tiziana Margaria
Efficient test-based model generation for legacy reactive systems. 95-100 - Samar Abdi, Daniel Gajski:
Model validation for mapping specification behaviors to processing elements. 101-106
Fault Coverage Analysis
- Ahmad A. Al-Yamani, Edward J. McCluskey:
Test quality for high level structural test. 109-114 - Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu:
On code coverage measurement for Verilog-A. 115-120 - Xiao Liu, Michael S. Hsiao:
On identifying functionally untestable transition faults. 121-126
SAT Solving Approaches
- Rajat Arora, Michael S. Hsiao:
CNF formula simplification using implication reasoning. 129-134 - Vijay Durairaj, Priyank Kalla:
Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis. 135-140 - Vijay Durairaj, Priyank Kalla:
Exploiting hypergraph partitioning for efficient Boolean satisfiability. 141-146
Validation of Network Architectures
- Calin Ciordas, Twan Basten
An event-based network-on-chip monitoring service. 149-154 - Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-based power/performance analysis of network processor architectures. 155-160 - Fulvio Corno
Validation of the dependability of CAN-based networked systems. 161-164
High-Level Validation
- Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama:
High level hardware validation using hierarchical message sequence charts. 167-172 - Daniel Gil, Joaquin Gracia, Juan Carlos Baraza
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques. 173-178 - Masahiro Fujita:
On equivalence checking between behavioral and RTL descriptions. 179-184
Panel
- Harry Foster:
Panel: Driving the intelligent testbanch: are we there yet? 188 - Gary Smith:
Panel: What happened to the intelligent test bench? 189
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