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Robert Michael Owens
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2000 – 2009
- 2000
- [j35]Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The design of the MGAP-2: a micro-grained massively parallel array. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 709-716 (2000)
1990 – 1999
- 1999
- [j34]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
A Fast and Simple Steiner Routing Heuristic. Discret. Appl. Math. 90(1-3): 51-67 (1999) - [j33]Benjamin Bishop, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
Aggressive Dynamic Execution of Decoded Traces. J. VLSI Signal Process. 22(1): 65-75 (1999) - 1998
- [j32]Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens:
A Parallel ASIC Architecture for Efficient Fractal Image Coding. J. VLSI Signal Process. 19(2): 97-113 (1998) - [j31]Robert Michael Owens, Mohan Vishwanath:
A Very Efficient Storage Structure for DWT and IDWT Filters. J. VLSI Signal Process. 19(3): 215-225 (1998) - [c68]Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa:
Validation of an Architectural Level Power Analysis Technique. DAC 1998: 242-245 - [c67]Benjamin Bishop, Robert Michael Owens, Mary Jane Irwin:
Aggressive Dynamic Execution of Multimedia Kernel Traces. IPPS/SPDP 1998: 640-646 - 1997
- [j30]Meng-Fan Chang, Mary Jane Irwin, Robert Michael Owens:
Power-Area Trade-Offs in Divided Word Line Memory Arrays. J. Circuits Syst. Comput. 7(1): 49-68 (1997) - [j29]Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
Motion Analysis on the Micro Grained Array Processor. Real Time Imaging 3(2): 101-110 (1997) - [j28]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
A fast algorithm for minimizing the Elmore delay to identified critical sinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 753-759 (1997) - [c66]Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The MGAP Family of Processor Arrays. Great Lakes Symposium on VLSI 1997: 105- - [c65]Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin:
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. Great Lakes Symposium on VLSI 1997: 182- - [c64]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Mixed-autonomy local interconnect for reconfigurable SIMD arrays. HiPC 1997: 428-431 - [c63]Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh:
Techniques for low energy software. ISLPED 1997: 72-75 - [c62]Patrick Hicks, Matthew Walnock, Robert Michael Owens:
Analysis of power consumption in memory hierarchies. ISLPED 1997: 239-242 - [c61]Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
A Simulation Methodology for Software Energy Evaluation. VLSI Design 1997: 509-510 - 1996
- [j27]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for low power CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 665-671 (1996) - [j26]Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. 13(1): 67-75 (1996) - [j25]Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens:
Architectures for wavelet transforms: A survey. J. VLSI Signal Process. 14(2): 171-192 (1996) - [c60]Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
An Architectural Design For Parallel Fractal Compression. ASAP 1996: 3-11 - [c59]Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga:
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. ASAP 1996: 65-71 - [c58]Mohan Vishwanath, Robert Michael Owens:
A Common Architecture For The DWT and IDWT. ASAP 1996: 193-198 - [c57]Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
Energy Characterization based on Clustering. DAC 1996: 702-707 - [c56]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Recent Developments in Performance Driven Steiner Routing: An Overview. Great Lakes Symposium on VLSI 1996: 137-142 - [c55]Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
Some Issues in Gray Code Addressing. Great Lakes Symposium on VLSI 1996: 178-181 - [c54]Raminder Singh Bajwa, Robert Michael Owens, Thomas P. Kelliher:
Simultaneous speech segmentation and phoneme recognition using dynamic programming. ICASSP 1996: 3213-3216 - [c53]Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
Instruction level power profiling. ICASSP 1996: 3326-3329 - [c52]Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens:
Power comparisons for barrel shifters. ISLPED 1996: 209-212 - [c51]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Design tradeoffs in high speed multipliers and FIR filters. VLSI Design 1996: 29-32 - 1995
- [j24]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. 9(3): 193-209 (1995) - [c50]Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin:
Reducing the number of counters needed for integer multiplication. IEEE Symposium on Computer Arithmetic 1995: 38-41 - [c49]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
The MGAP's programming environment and the *C++ language. ASAP 1995: 121-124 - [c48]Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
Motion Estimation Algorithms on Fine Grain Array Processor. ASAP 1995: 204-213 - [c47]Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Accurate Estimation of Combinational Circuit Activity. DAC 1995: 618-622 - [c46]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Fast algorithm for performance-oriented Steiner routing. Great Lakes Symposium on VLSI 1995: 198-203 - [c45]Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens:
A survey of architectures for the discrete and continuous wavelet transforms. ICASSP 1995: 2849-2852 - [c44]Thomas P. Kelliher, Eric Gayles, Robert Michael Owens, Mary Jane Irwin:
The MGAP-2: an advanced, massively parallel VLSI signal processor. ICASSP 1995: 3219-3222 - [c43]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Unifying carry-sum and signed-digital number representations for low power. ISLPD 1995: 15-20 - [c42]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
High-throughput and low-power DSP using clocked-CMOS circuitry. ISLPD 1995: 139-144 - [c41]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. ISLPD 1995: 167-172 - [c40]Paul Keltcher, Robert Michael Owens, Mary Jane Irwin:
A simulation methodology for evaluating parallel computers. SPDP 1995: 478-481 - [c39]Manjit Borah, Mary Jane Irwin, Robert Michael Owens:
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. VLSI Design 1995: 294-298 - 1994
- [j23]Gueesang Lee, Mary Jane Irwin, Robert Michael Owens:
Polynomial Time Testability of Circuits Generated by Input Decomposition. IEEE Trans. Computers 43(2): 201-210 (1994) - [j22]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. IEEE Trans. Computers 43(10): 1121-1128 (1994) - [j21]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang:
Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1280-1287 (1994) - [j20]Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
An edge-based heuristic for Steiner routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1563-1568 (1994) - [j19]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Power-delay characteristics of CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 377-381 (1994) - [c38]Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin:
FPGA-based synthesis of FSMs through decomposition. Great Lakes Symposium on VLSI 1994: 97-100 - [c37]Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) 1994: 96-104 - [c36]Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens:
Digit pipelined discrete wavelet transform. ICASSP (2) 1994: 405-408 - [c35]Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens, Chen-Mi Wu:
Dynamic Space Warping Algorithms on Fine-Graln Array Processors. IPPS 1994: 921-925 - 1993
- [j18]Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 491-502 (1993) - [c34]Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Digit systolic algorithms for fine-grain architectures. ASAP 1993: 466-477 - [c33]Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin:
Multi-way FSM decomposition based on interconnect complexity. EURO-DAC 1993: 390-395 - [c32]Chen-Mi Wu, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
A new blocked IIR algorithm. ICASSP (3) 1993: 113-116 - [c31]Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
Edge detection using fine-grained parallelism in VLSI. ICASSP (1) 1993: 401-404 - [c30]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
Image Processing with the MGAP: A Cost Effective Solution. IPPS 1993: 439-443 - [c29]Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
A Massively Parallel, Micro-Grained VLSI Architecture. VLSI Design 1993: 250-255 - 1992
- [j17]Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang:
ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41(9): 1181-1184 (1992) - [j16]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 545-554 (1992) - [c28]Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa:
Implementing a family of high performance, micrograined architectures. ASAP 1992: 191-205 - [c27]Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
Discrete wavelet transforms in VLSI. ASAP 1992: 218-229 - [c26]Soohong Kim, Robert Michael Owens, Mary Jane Irwin:
Experiments with a Performance Driven Module Generator. DAC 1992: 687-690 - [c25]Soohong Kim, Robert Michael Owens, Mary Jane Irwin:
PERFLEX: a performance driven module generator. EURO-DAC 1992: 154-159 - [c24]Mary Jane Irwin, Robert Michael Owens:
A micro-grained VLSI signal processor. ICASSP 1992: 641-644 - [c23]Mohan Vishwanath, Robert Michael Owens:
An AT2 lower bound for wavelet transforms in VLSI. ICASSP 1992: 649-652 - [c22]Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra. VLSI Design 1992: 221-226 - 1991
- [j15]Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin:
Digit Serial Multipliers. J. Parallel Distributed Comput. 11(2): 156-162 (1991) - [j14]Mary Jane Irwin, Robert Michael Owens:
A Two-Dimensional, Distributed Logic Architecture. IEEE Trans. Computers 40(10): 1094-1101 (1991) - [c21]Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
The Arithmetic Cube: error analysis and simulation. ASAP 1991: 129-143 - [c20]Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, Kin-Ki Leung, Mohan Vishwanath:
The arithmetic cube II: a second generation VLSI DSP processor. ICASSP 1991: 1125-1128 - 1990
- [j13]Robert Michael Owens, Mary Jane Irwin:
Being Stingy with Multipliers. IEEE Trans. Computers 39(6): 809-818 (1990) - [j12]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1017-1027 (1990) - [j11]Mary Jane Irwin, Robert Michael Owens:
A case for digit serial VLSI signal processors. J. VLSI Signal Process. 1(4): 321-334 (1990) - [c19]Chen-Mie Wu, Robert Michael Owens, Mary Jane Irwin:
Mapping high-dimension wavefront computations to silicon. ASAP 1990: 78-89 - [c18]Mary Jane Irwin, Robert Michael Owens:
A two-dimensional, distributed logic processor for machine vision. ICASSP 1990: 945-948 - [c17]Chen-Mi Wu, Robert Michael Owens, Mary Jane Irwin:
Distortion processing in image matching problems. ICASSP 1990: 2181-2184 - [c16]Gueesang Lee, Mary Jane Irwin, Robert Michael Owens:
Test generation in circuits constructed by input decomposition. ICCD 1990: 107-111 - [c15]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Logic synthesis for programmable logic devices. ICCD 1990: 364-367 - [c14]Barry M. Pangrle, Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin:
An integrated, multi-level synthesis system. RSP 1990: 167-175
1980 – 1989
- 1989
- [c13]TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Multi-Level Logic Synthesis Using Communication Complexity. DAC 1989: 215-220 - [c12]Mary Jane Irwin, Robert Michael Owens:
A Comparison of Four Two-dimensional Gate Matrix Layout Tools. DAC 1989: 698-701 - [c11]Robert Michael Owens, Mary Jane Irwin:
Implementing algorithms for convolution on arrays of adders. ICASSP 1989: 1127-1130 - 1988
- [c10]Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin:
DECOMPOSER: A Synthesizer for Systolic Systems. DAC 1988: 650-653 - [c9]Robert Michael Owens, Mary Jane Irwin:
Multidimensional algorithms for VLSI processors. ICASSP 1988: 749-752 - [c8]Mary Jane Irwin, Robert Michael Owens:
A comparison of two digit serial VLSI adders. ICCD 1988: 227-229 - 1987
- [j10]Mary Jane Irwin, Robert Michael Owens:
Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial. Computer 20(4): 61-73 (1987) - [j9]Robert Michael Owens, Mary Jane Irwin:
The Arithmetic Cube. IEEE Trans. Computers 36(11): 1342-1348 (1987) - [j8]Mary Jane Irwin, Robert Michael Owens:
Digit pipelined processors. J. Supercomput. 1(1): 61-86 (1987) - [c7]Poras T. Balsara, Robert Michael Owens:
Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic 1987: 169-173 - [c6]Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin:
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. DAC 1987: 357-362 - [c5]Robert Michael Owens, Mary Jane Irwin:
An Overview of the Penn State Design System. DAC 1987: 516-522 - 1986
- [j7]Robert Michael Owens, Mary Jane Irwin:
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3): 420-428 (1986) - [j6]Robert Michael Owens, Joseph F. JáJá:
A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform. IEEE Trans. Acoust. Speech Signal Process. 34(4): 979-989 (1986) - [c4]Robert Michael Owens, Joseph F. JáJá:
Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories. ICPP 1986: 812-818 - 1985
- [j5]Robert Michael Owens, Joseph F. JáJá:
Parallel Sorting with Serial Momories. IEEE Trans. Computers 34(4): 379-383 (1985) - 1984
- [j4]Joseph F. JáJá, Robert Michael Owens:
VLSI Sorting with Reduced Hardware. IEEE Trans. Computers 33(7): 668-671 (1984) - 1983
- [j3]Joseph F. JáJá, Robert Michael Owens:
An architecture for a VLSI FFT processor. Integr. 1(4): 305-316 (1983) - [j2]Mary Jane Irwin, Robert Michael Owens:
Fully Digit On-Line Networks. IEEE Trans. Computers 32(4): 402-406 (1983) - [j1]Robert Michael Owens:
Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic. IEEE Trans. Computers 32(4): 406-411 (1983) - [c3]Robert Michael Owens, Mary Jane Irwin:
Numerical limitations on the design of digit online networks. IEEE Symposium on Computer Arithmetic 1983: 156-161 - 1981
- [c2]Robert Michael Owens:
Compound algorithms for digit online arithmetic. IEEE Symposium on Computer Arithmetic 1981: 64-71
1970 – 1979
- 1979
- [c1]Robert Michael Owens, Mary Jane Irwin:
On-Line Algorithms for the Design of Pipeline Architectures. ISCA 1979: 12-19
Coauthor Index
[j35] [j34] [j33] [j32] [c68] [c67] [j30] [j29] [j28] [c66] [c65] [c64] [c63] [c61] [j27] [j26] [c60] [c59] [c57] [c56] [c55] [c53] [c52] [c51] [j24] [c50] [c49] [c48] [c47] [c46] [c44] [c43] [c42] [c41] [c40] [c39] [j23] [j22] [j21] [j20] [j19] [c38] [c37] [c36] [c35] [j18] [c34] [c33] [c32] [c31] [c30] [c29] [j17] [j16] [c28] [c27] [c26] [c25] [c24] [c22] [j15] [j14] [c21] [c20] [j13] [j12] [j11] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [j10] [j9] [j8] [c6] [c5] [j7] [j2] [c3] [c1]
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