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Masanori Natsui
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2020 – today
- 2024
- [j15]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. 107(8): 958-965 (2024) - [c39]Fangcen Zhong, Masanori Natsui, Takahiro Hanyu:
Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. IJCNN 2024: 1-7 - [c38]Masanori Natsui, Ken Asano, Takahiro Hanyu:
Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic. ISMVL 2024: 42-46 - [c37]Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu:
Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme. MWSCAS 2024: 1257-1261 - 2023
- [c36]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS 2023: 1-4 - [c35]Fangcen Zhong, Masanori Natsui, Takahiro Hanyu:
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS 2023: 1-5 - [c34]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL 2023: 7-11 - [c33]Kaede Sakai, Masanori Natsui, Takahiro Hanyu:
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS 2023: 269-273 - 2022
- [c32]Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu:
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS 2022: 1-4 - 2021
- [j14]Masanori Natsui
, Akira Tamakoshi
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - 2020
- [c31]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j13]Masanori Natsui
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [c30]Tomoki Chiba, Masanori Natsui, Takahiro Hanyu:
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL 2019: 91-96 - [c29]Masanori Natsui
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - 2018
- [j12]Masanori Natsui
Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. 82: 13-21 (2018) - [c28]Hiroki Suda, Masanori Natsui
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL 2018: 56-61 - 2017
- [c27]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE 2017: 548-553 - 2016
- [j11]Takahiro Hanyu
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c26]Masanori Natsui
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - [c25]Naoto Sugaya, Masanori Natsui
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL 2016: 72-77 - [c24]Masanori Natsui
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS 2016: 1-4 - 2015
- [j10]Masanori Natsui
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - [c23]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE 2015: 1006-1011 - [c22]Takeaki Akutsu, Masanori Natsui
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL 2015: 152-157 - [c21]Daisuke Suzuki, Masanori Natsui
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - 2014
- [j9]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [c20]Masanori Natsui
Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL 2014: 243-247 - [c19]Masanori Natsui
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS 2014: 468 - 2013
- [j8]Daisuke Suzuki, Masanori Natsui
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013) - [j7]Masanori Natsui, Takahiro Hanyu:
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. 21(5-6): 597-608 (2013) - [c18]Masanori Natsui
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - [c17]Masanori Natsui
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL 2013: 146-151 - [c16]Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j6]Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu:
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. 19(1-3): 219-231 (2012) - [c15]Shoun Matsunaga, Masanori Natsui
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476 - [c14]Youngkeun Kim, Masanori Natsui
Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS 2012: 2705-2708 - [c13]Masanori Natsui
Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL 2012: 214-219 - [c12]Daisuke Suzuki, Masanori Natsui
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. MWSCAS 2012: 334-337 - [c11]Masanori Natsui
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. NEWCAS 2012: 97-100 - 2011
- [j5]Takayuki Konishi, Kenji Inazu, Jun Gyu Lee, Masanori Natsui
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology. IEICE Trans. Electron. 94-C(3): 334-345 (2011) - [c10]Shoun Matsunaga, Akira Katsumata, Masanori Natsui
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL 2011: 99-104 - 2010
- [j4]Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. 93-D(8): 2080-2088 (2010) - [c9]Masanori Natsui
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL 2010: 235-240
2000 – 2009
- 2009
- [c8]Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL 2009: 60-65 - 2008
- [c7]Masanori Natsui, Yoshiaki Tadokoro:
Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure. ICINCO-ICSO 2008: 193-199 - 2007
- [j3]Masanori Natsui
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. IEICE Electron. Express 4(3): 88-93 (2007) - 2006
- [c6]Masanori Natsui, Shunichi Kubo, Yoshiaki Tadokoro:
GA-based approach to pitch recognition of musical consonance. ICINCO-SPSMC 2006: 47-54 - [c5]Yoshiaki Tadokoro, Masanori Natsui, Yasuhiro Seto, Michiru Yamaguchi:
Pitch estimation of difficult polyphony sounds overlapping some frequency components. ICINCO-SPSMC 2006: 168-176 - 2005
- [j2]Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. J. Multiple Valued Log. Soft Comput. 11(5-6): 519-544 (2005) - 2004
- [c4]Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN 2004: 342-351 - 2003
- [c3]Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation 2003: 115-122 - 2002
- [j1]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(9): 2061-2071 (2002) - [c2]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. ISMVL 2002: 96-103 - 2001
- [c1]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. ISMVL 2001: 253-258
Coauthor Index
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last updated on 2024-10-11 17:26 CEST by the dblp team
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