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48th ISMVL 2018: Linz, Austria
- 48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, Linz, Austria, May 16-18, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-4464-5
Session 1A: Quaternary Logic
- Radomir S. Stankovic, Milena Stankovic, Jaakko Astola, Claudio Moraga:
Quaternary Generalized Boolean Bent Functions Obtained Through Permutation of Binary Boolean Bent Functions. 1-6 - Manami Suzuki, Rei Ueno, Naofumi Homma, Takafumi Aoki:
Quaternary Debiasing for Physically Unclonable Functions. 7-12 - Ivan Prokic
:
Characterization of Quaternary Threshold Functions in the Vilenkin-Chrestenson Basis. 13-18
Session 1B: Multiple-Valued Hardware
- Jozef Kostolny, Elena Zaitseva
Application of Multiple-Valued Logic in Importance Analysis of k-out-of-n Multi-state Systems. 19-24 - Takao Waho:
An Analog-to-Digital Converter Using Delta-Sigma Modulator Network. 25-30 - Elena Dubrova:
A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks. 31-37
Session 2A: Multiple-Valued Functions
- Sumanta Chaudhuri:
Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices. 38-43 - Shima Sedighiani, Arman Kazemi
An Energy-Efficient Quaternary Serial Adder for Nanoelectronics. 44-49 - Tsutomu Sasao:
On a Memory-Based Realization of Sparse Multiple-Valued Functions. 50-55
Session 2B: Security and More
- Hiroki Suda, Masanori Natsui
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. 56-61 - Akira Ito, Rei Ueno, Naofumi Homma, Takafumi Aoki:
On the Detectability of Hardware Trojans Embedded in Parallel Multipliers. 62-67 - Jan Malburg, Heinz Riener, Görschwin Fey
Mining Latency Guarantees for RTL Designs. 68-73
Session 3A: Algebra and Theory
- Damián Enrique Szmuc
Track-Down Operations on Bilattices. 74-79 - Hajime Machida, Jovanka Pantovic:
One Class of Maximal Binary Monomials. 80-84 - Hajime Machida, Ivo G. Rosenberg:
Commutation for Functions of Small Arity Over a Finite Set. 85-90 - Jan Paseka
A Representation Theorem for Quantale Valued sup-algebras. 91-96
Session 3B: Reversible Circuits
- Zaid Al-Wardi
Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. 97-102 - Alexandre A. A. de Almeida
Reversible Circuit Optimization Based on Tabu Search. 103-108 - Pawel Kerntopf, Radomir S. Stankovic, Krzysztof Podlaski
Ternary/MV Reversible Functions with Component Functions from Different Equivalence Classes. 109-114 - Alwin Zulehner, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Robert Wille:
Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-Valued Logic. 115-120
Session 4A: New Technologies and Applications
- Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
Logic Design Using Memristors: An Emerging Technology. 121-126 - Kenta Saito, Naoki Suefuji, Seiya Kasai, Masashi Aono
Amoeba-Inspired Electronic Solution-Searching System and Its Application to Finding Walking Maneuver of a Multi-legged Robot. 127-131 - Naotake Kamiura, Takayuki Yumoto, Teijiro Isokawa:
Specific Health Examination Data Prediction for Female Subjects with Unhealthy-Level Visceral Fat Using Self-Organizing Maps. 132-137
Session 4B: Index Functions and Algebra
- Jon T. Butler, Tsutomu Sasao:
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. 138-143 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. 144-149 - Guillermo Badia, Carles Noguera
Saturated Models in Mathematical Fuzzy Logic. 150-155
Session 5A: Design of Multiple- Valued Circuits I
- Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu:
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. 156-161 - Micah Thornton, Mitchell A. Thornton:
Multiple-Valued Random Digit Extraction. 162-167 - Milos Radmanovic, Radomir S. Stankovic:
Generating Synthetic MVL Benchmarks from Random MDDs Under Restrictions. 168-173
Session 5B: Neural Networks
- Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. 174-179 - Maurice Yang, Mahmoud Faraj, Assem S. Hussein, Vincent C. Gaudet
Efficient Hardware Realization of Convolutional Neural Networks Using Intra-Kernel Regular Pruning. 180-185 - Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama:
CNOT-Measure Quantum Neural Networks. 186-191
Session 6A: Design of Multiple-Valued Circuits II
- Chetan Vudadha, M. B. Srinivas:
Design Methodologies for Ternary Logic Circuits. 192-197 - D. Michael Miller, Mathias Soeken:
A Spectral Algorithm for Ternary Function Classification. 198-203 - Anmol Prakash Surhonne, Debjyoti Bhattacharjee
Synthesis of Multi-valued Literal Using Lukasiewicz Logic. 204-209
Session 6B: Circuits and Signals
- Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima, Yasushi Yuminaka
Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test. 210-214 - Mohammad Mahmoud A. Taha
Realization of Arithmetic Operators Based on Stochastic Number Frequency Signal Representation. 215-220 - Maciej Rudziecki:
Algebra of Transient States of Postan Signals. 221-228
Session 7A: Reed-Muller and Spectral
- Tamás Waldhauser:
On the Number of Fixed Points of the Reed-Muller-Fourier Transform. 229-234 - Milena Stankovic, Claudio Moraga, Radomir S. Stankovic:
Generation of Ternary Bent Functions by Spectral Invariant Operations in the Generalized Reed-Muller Domain. 235-240 - Claudio Moraga, Radomir S. Stankovic, Jaakko Astola:
On the Reed-Muller-Fourier Spectrum of Multiple-Valued Rotation Symmetric Functions. 241-246
Session 7B: Quantum
- Miroslav Saraivanov, Marek A. Perkowski:
Multi-valued Quantum Cascade Realization with Group Decomposition. 247-253 - Wouter Castryck
Translating Between the Roots of the Identity in Quantum Computers. 254-259 - Kaitlin N. Smith, Tim LaFave, Duncan L. MacFarlane, Mitchell A. Thornton:
A Radix-4 Chrestenson Gate for Optical Quantum Computation. 260-265
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