default search action
ICCAD 2014: San Jose, California, USA
- Yao-Wen Chang:
The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014. IEEE 2014, ISBN 978-1-4799-6277-8
Enhancing correctness of advanced design
- Eli Arbel, Shlomit Koyfman, Prabhakar Kudva, Shiri Moran:
Automated detection and verification of parity-protected memory elements. 1-8 - Li Lei, Kai Cong, Zhenkun Yang, Fei Xie:
Validating direct memory access interfaces with conformance checking. 9-16 - Eric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
Data-parallel simulation for fast and accurate timing validation of CMOS circuits. 17-23
CAD for next-generation vehicles
- Chung-Wei Lin, Qi Zhu
, Alberto L. Sangiovanni-Vincentelli:
Security-aware mapping for TDMA-based real-time distributed systems. 24-31 - Xue Lin, Yanzhi Wang, Paul Bogdan
Reinforcement learning based power management for hybrid electric vehicles. 32-38 - Arquimedes Canedo, Jiang Wan, Mohammad Abdullah Al Faruque
Functional modeling compiler for system-level design of automotive cyber-physical systems. 39-46
Emerging reconfigurable array technologies
- Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian:
BDD-based synthesis of reconfigurable single-electron transistor arrays. 47-54 - Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu
Architecting 3D vertical resistive memory for next-generation storage systems. 55-62 - Beiye Liu, Hai Li, Yiran Chen, Xin Li, Tingwen Huang, Qing Wu, Mark Barnell:
Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. 63-70
Challenges and techniques for high level design
- Ruchir Puri:
Application driven high level design in the era of heterogeneous computing. 71 - Yatin Hoskote, Ilya Klotchkov:
High level design for wearables and IoT. 72 - Nagu R. Dhanwada, William Rhett Davis
Towards a standard flow for system level power modeling. 73
Adaptive designs in computing, power management and communication for low-power circuits and systems with ultra-wide dynamic ranges
- Arijit Raychowdhury, Saad Bin Nasir
The role of adaptation and resiliency in computation and power management. 74-79 - Shreyas Sen:
Channel-adaptive zero-margin & process-adaptive self-healing communication circuits/systems. 80-85
Design, modeling and tools for video analytics using emerging devices
- Yan Fang, Victor V. Yashin
Modeling oscillator arrays for video analytic applications. 86-91 - Indranil Palit, Qiuwen Lou, Michael T. Niemier, Behnam Sedighi, Joseph Nahas, Xiaobo Sharon Hu
Cellular neural networks for image analysis using steep slope devices. 92-95 - Matthew Cotter, Siddharth Advani, Jack Sampson, Kevin M. Irick, Vijaykrishnan Narayanan:
A hardware accelerated multilevel visual classifier for embedded visual-assist systems. 96-100
Patterns and placement
- Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang:
DRC-based hotspot detection considering edge tolerance and incomplete specification. 101-107 - Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
Triple patterning lithography aware optimization for standard cell based design. 108-115 - Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong
Triple patterning aware detailed placement with constrained pattern assignment. 116-123 - Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi:
Sub-20 nm design technology co-optimization for standard cell logic. 124-131
Energy, performance and security for embedded systems
- Felipe Sampaio, Muhammad Shafique
Energy-efficient architecture for advanced video memory. 132-139 - Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang:
Compaction-free compressed cache for high performance multi-core system. 140-147 - Wenjie Che
A non-volatile memory based physically unclonable function without helper data. 148-153 - Gokhan Sayilar, Derek Chiou:
Cryptoraptor: high throughput reconfigurable cryptographic processor. 154-161
Can one shield integrated circuits and systems from supply chain attacks?
- Siam U. Hussain, Sudha Yellapantula, Mehrdad Majzoobi, Farinaz Koushanfar
BIST-PUF: online, hardware-based evaluation of physically unclonable circuit identifiers. 162-169 - Davood Shahrjerdi, Jeyavijayan Rajendran, Siddharth Garg, Farinaz Koushanfar
Shielding and securing integrated circuits with sensors. 170-174
Smart energy system: electric vehicle, home, HVAC, hybrid system and cybersecurity
- Naehyuck Chang, Donkyu Baek, Jeongmin Hong:
Power consumption characterization, modeling and estimation of electric vehicles. 175-182 - Yang Liu, Shiyan Hu, Tsung-Yi Ho
Vulnerability assessment and defense technology for smart home cybersecurity considering pricing cyberattacks. 183-190 - Tianshu Wei, Qi Zhu
Co-scheduling of HVAC control, EV charging and battery usage for building energy efficiency. 191-196 - Jie Wu, Jinjun Xiong
Real time anomaly detection in wide area monitoring of smart grids. 197-204
Analysis and optimization of timing, noise, and power
- Tao Wang, Chun Zhang, Jinjun Xiong
Variation aware optimal threshold voltage computation for on-chip noise sensors. 205-212 - Shu-Hung Lin, Mark Po-Hung Lin
More effective power-gated circuit optimization with multi-bit retention registers. 213-217 - Xueqian Zhao, Zhuo Feng, Cheng Zhuo:
An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids. 218-223 - Hantao Huang, Sai Manoj Pudukotai Dinakarrao
Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication. 224-229
What is behind the mask?
- Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang
Fast lithographic mask optimization considering process variation. 230-237 - Ahmed Awad, Atsushi Takahashi
A fast process variation and pattern fidelity aware mask optimization algorithm. 238-245 - Tuck-Boon Chan, Puneet Gupta
Benchmarking of mask fracturing heuristics. 246-253 - Jian Kuang, Evangeline F. Y. Young:
Overlapping-aware throughput-driven stencil planning for E-beam lithography. 254-261
Detection & prevention of IC security threats
- Stephen M. Plaza, Igor L. Markov:
Protecting integrated circuits from piracy with test-aware logic locking. 262-269 - James B. Wendt, Miodrag Potkonjak:
Hardware obfuscation using PUF-based logic. 270-277 - Jie Zhang, Guantong Su, Yannan Liu, Lingxiao Wei, Feng Yuan, Guoqiang Bai, Qiang Xu
On trojan side channel design and identification. 278-285
Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip
- Krishnendu Chakrabarty
Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip. 286-288
Runtime optimizations for emerging memory and on-chip systems
- Animesh Jain, Ritesh Parikh, Valeria Bertacco:
High-radix on-chip networks with low-radix routers. 289-294 - Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. 295-300 - Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie:
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. 301-308
Noise and variability
- Ahmet Gokcen Mahmutoglu, Alper Demir
Modeling and analysis of nonstationary low-frequency noise in circuit simulators: enabling non monte carlo techniques. 309-315 - Manzil Zaheer
MPME-DP: multi-population moment estimation via dirichlet process for efficient validation of analog/mixed-signal circuits. 316-323 - Shupeng Sun, Xin Li:
Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space. 324-331
Advanced verification and diagnosis techniques
- Stephen Longfield Jr., Rajit Manohar:
Removing concurrency for rapid functional verification. 332-339 - Nian-Ze Lee
Towards formal evaluation and verification of probabilistic design. 340-347 - Charlie Shucheng Zhu, Georg Weissenbacher
Silicon fault diagnosis using sequence interpolation with backbones. 348-355
2014 CAD contest
- Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li:
The overview of 2014 CAD contest at ICCAD. 356 - Chih-Jen Hsu, Wei-Hsun Lin, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite. 357-360 - Myung-Chul Kim, Jin Hu, Natarajan Viswanathan:
ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite. 361-366 - Rasit Onur Topaloglu
ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite. 367-368
Emerging applications of networked cyberphysical systems
- Shuang Chen, Yanzhi Wang, Massoud Pedram:
Optimal offloading control for a mobile device based on a realistic battery model and semi-markov decision process. 369-375 - Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou:
A learning-on-cloud power management policy for smart devices. 376-381 - Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes:
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. 382-388
Routing in EDA and beyond
- Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang:
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. 389-396 - Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li:
MCFRoute: a detailed router based on multi-commodity flow method. 397-404 - Oliver Keszöcze
Exact routing for digital microfluidic biochips with temporary blockages. 405-410
CAD for the internet of things
- Gang Qu, Lin Yuan:
Design things for the internet of things: an EDA perspective. 411-416 - Teng Xu, James B. Wendt, Miodrag Potkonjak:
Security of IoT systems: design challenges and opportunities. 417-423 - Chenguang Shen, Haksoo Choi, Supriyo Chakraborty, Mani B. Srivastava
Towards a rich sensing stack for IoT devices. 424-427
Full-chip electromigration assessment and system-level EM reliability management
- Valeriy Sukharev
IR-drop based electromigration assessment: parametric failure chip-scale analysis. 428-433 - Taeyoung Kim
Lifetime optimization for real-time embedded systems considering electromigration effects. 434-439 - Marko Chew, Ara Aslyan, Jun-Ho Choy, Xin Huang:
Accurate full-chip estimation of power map, current densities and temperature for EM assessment. 440-445
Advances in logic synthesis
- Zhao Wang, Xiao He, Carl M. Sechen:
TonyChopper: a desynchronization package. 446-453 - Michael Wang, Andrew Yates, Igor L. Markov:
SuperPUF: integrating heterogeneous physically unclonable functions. 454-461 - Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne:
Constrained interpolation for guided logic synthesis. 462-469 - Anika Raghuvanshi, Marek A. Perkowski:
Logic synthesis and a generalized notation for memristor-realized material implication gates. 470-477
How to keep chip aging at bay
- Hussam Amrouch
Towards interdependencies of aging mechanisms. 478-485 - Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis
A systematic approach for analyzing and optimizing cell-internal signal electromigration. 486-491 - Deepashree Sengupta, Sachin S. Sapatnekar
ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI. 492-497 - Michihiro Shintani
Sensorless estimation of global device-parameters based on Fmax testing. 498-503
Approximate and stochastic circuits
- Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Multi-level approximate logic synthesis under general error constraints. 504-510 - Li Li, Hai Zhou:
On error modeling and analysis of approximate adders. 511-518 - Yili Ding, Yi Wu, Weikang Qian:
Generating multiple correlated probabilities for MUX-based stochastic computing architecture. 519-526
Cool technologies for cool chips
- Arvind Sridhar, Mohamed M. Sabry, Patrick W. Ruch
PowerCool: simulation of integrated microfluidic power generation in bright silicon MPSoCs. 527-534 - Sri Harsha Choday, Kon-Woo Kwon, Kaushik Roy:
Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting. 535-541 - Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, Shu-Fei Tsai:
Fast and accurate emissivity and absolute temperature maps measurement for integrated circuits. 542-549
Design and CAD to enable 3D integration
- Wei-Che Wang, Puneet Gupta
Efficient layout generation and evaluation of vertical channel devices. 550-556 - Christopher Condrat, Priyank Kalla, Steve Blair:
Thermal-aware synthesis of integrated photonic ring resonators. 557-564 - Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim
Full chip impact study of power delivery network designs in monolithic 3D ICs. 565-572
DFM for extreme technology nodes
- Luigi Capodieci:
Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodes. 573 - Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang:
Design and manufacturing process co-optimization in nano-technology. 574-581 - Lars W. Liebmann, Rasit Onur Topaloglu
Design and technology co-optimization near single-digit nodes. 582-585
Automated and quality-driven requirement engineering
- Rolf Drechsler
Automated and quality-driven requirements engineering. 586-590
Pessimism removal during timing analysis
- Jin Hu, Debjit Sinha, Igor Keller:
TAU 2014 contest on removing common path pessimism during timing analysis. 591 - Vibhor Garg:
Common path pessimism removal: an industry perspective. 592-595 - Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
Fast path-based timing analysis for CPPR. 596-599 - Yu-Ming Yang, Yu-Wei Chang, Iris Hui-Ru Jiang:
iTimerC: common path pessimism removal using effective reduction methods. 600-605 - Christos Kalonakis, Charalampos Antoniadis
TKtimer: fast & accurate clock network pessimism removal. 606-610
Emulation, modeling and simulation of analog systems
- Haotian Liu, Kim Batselier
A novel linear algebra method for the determination of periodic steady states of nonlinear oscillators. 611-617 - Ya Wang, Peng Li, Suming Lai:
A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC converters. 618-625 - Moning Zhang, Yang Tang, Zuochang Ye:
Large-signal MOSFET modeling using frequency-domain nonlinear system identification. 626-632 - Frank Austin Nothaft
Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models. 633-640
Advanced placement
- Gang Wu, Tao Lin, Hsin-Ho Huang, Chris Chu, Peter A. Beerel:
Asynchronous circuit placement by lagrangian relaxation. 641-646 - Yu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang
Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. 647-654 - Javier de San Pedro
A hierarchical approach for generating regular floorplans. 655-662 - Hsin-Chun Lin, Shih-Ying Sean Liu, Hung-Ming Chen:
Planning and placing power clamps for effective CDM protection. 663-669
Advances in debug and formal verification
- Kuo-Kai Hsieh, Wen Chen, Li-C. Wang
On application of data mining in functional debug. 670-675 - Miroslav N. Velev
Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinality. 676-683 - Djordje Maksimovic, Bao Le, Andreas G. Veneris:
Multiple clock domain synchronization in a QBF-based verification environment. 684-689 - Yang Zhao, Kristin Y. Rozier:
Probabilistic model checking for comparative analysis of automated air traffic control systems. 690-695
Mathematical methods for interconnect modeling and low power design
- Sai Manoj Pudukotai Dinakarrao
A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter. 696-701 - Wenjian Yu, Chao Zhang, Qing Wang, Yiyu Shi:
Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-vias. 702-709 - Debashis Banerjee, Barry John Muldrey
Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operation. 710-717
Software for management of parallelism and data integrity in embedded systems
- Mingxing Tan, Bin Liu, Steve Dai, Zhiru Zhang
Multithreaded pipeline synthesis for data-parallel kernels. 718-725 - Gaël Deest, Tomofumi Yuki, Olivier Sentieys, Steven Derrien:
Toward scalable source level accuracy analysis for floating-point to fixed-point conversion. 726-733 - Sheng-Wei Cheng, Yu-Fen Chang, Yuan-Hao Chang
Warranty-aware page management for PCM-based embedded systems. 734-741
Clock network design and timing
- Ying Teng, Baris Taskin:
Frequency-centric resonant rotary clock distribution network design. 742-749 - Umamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi:
Opportunistic through-silicon-via inductor utilization in LC resonant clocks: concept and algorithms. 750-757 - Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
UI-timer: an ultra-fast clock network pessimism removal algorithm. 758-765
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-22 18:47 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: