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13th FDL 2010: Southampton, UK
- Adam Morawiec, Jinnie Hinderscheit:
Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK. ECSI, Electronic Chips & Systems design Initiative 2010
LBSD1: Inheritance and Modelling
- Jon Pérez, Carlos Fernando Nicolás, Roman Obermaisser, Christian El Salloum:
Modeling Time-Triggered Architecture Based Safety-Critical Embedded Systems Using SystemC. FDL 2010: 10-15 - David Rich:
A Solution to the Lack of Multiple Inheritance in SystemVerilog. FDL 2010: 16-21 - Jun Ye, QingPing Tan, Tun Li, Bin Wu, Yuanru Meng:
Feature-Oriented Refactoring Proposal for Transaction Level Models in SoCLib. FDL 2010: 22-27
ABD1: Formal Models for Verification and Debug
- Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz:
Complete Verification of Weakly Programmable IPs against Their Operational ISA Model. FDL 2010: 29-36 - Alexander Finder, Görschwin Fey:
Evaluating Debugging Algorithms from a Qualitative Perspective. FDL 2010: 37-42 - Matthias Büker, Kim Grüttner, Philipp A. Hartmann, Ingo Stierand:
Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks. FDL 2010: 43-48
LBSD2: Power and Performance Optimisation
- Peter Brunmayr, Jan Haase, Christoph Grimm:
A Tripartite System Level Design Approach for Design Space Exploration. FDL 2010: 50-55 - Kim Grüttner, Kai Hylla, Sven Rosinger, Wolfgang Nebel:
Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems. FDL 2010: 56-61 - Stefan Stattelmann, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
Reconstructing Line References from Optimized Binary Code for Source-Level Annotation. FDL 2010: 62-67
ABD Tutorial: Robustness
- Régis Leveugle:
Early Robustness Evaluation of Digital Integrated Systems. FDL 2010: 69-70 - André Sülflow:
Bounded Fault Tolerance Checking. FDL 2010: 71 - Barbara Jobstmann:
Robustness with Respect to Error Specifications. FDL 2010: 72
ABD+LBSD: Formal Models for Design Analysis
- Eugenio Villar, Fernando Herrera, Víctor Fernández:
Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. FDL 2010: 74-79 - Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault:
Formal Verification of Timed VHDL Programs. FDL 2010: 80-85 - André Seffrin, Alexander Biedermann, Sorin A. Huss:
Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. FDL 2010: 86-91 - Franco Fummi, Davide Quaglia, Francesco Stefanni, Giovanni Lovato:
Modeling of Communication Infrastructure for Design-Space Exploration. FDL 2010: 92-97
EAMS1: More SystemC for "More than Moore"
- Jan Haase, Mario Lang, Christoph Grimm:
Mixed-Level Simulation of Wireless Sensor Networks. FDL 2010: 99-104 - Chenxu Zhao, Tom J. Kazmierski:
SystemC-A Modelling of Mixed-Technology Systems with Distributed Behaviour. FDL 2010: 105-110 - Tobias Kirchner, Nico Bannow, Christian Kerstan, Christoph Grimm:
Mixed Signal Simulation with SystemC and Saber. FDL 2010: 111-116 - Jun Zhu, Ingo Sander, Axel Jantsch:
HetMoC: Heterogeneous Modelling in SystemC. FDL 2010: 117-122
LBSD3: Efficient Analysis and Simulation of SystemC Models
- Kevin Marquet, Bageshri Karkare, Matthieu Moy:
A Theoretical and Experimental Review of SystemC Front-ends. FDL 2010: 124-129 - Rauf Salimi Khaligh, Martin Radetzki:
A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. FDL 2010: 130-135 - Sébastien Le Nours, Anthony Barreteau, Olivier Pasquier:
Modeling Technique for Simulation Time Speed-up of Performance Computation in Transaction Level Models. FDL 2010: 136-141 - Mohammad Hosseinabady, José L. Núñez-Yáñez:
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL 2010: 142-147
EAMS2: Analog and Mixed-Technology System Design
- Bo Wang, Ian O'Connor, Emmanuel Drouard, Lioua Labrak:
Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System. FDL 2010: 149-154 - Marie Rouvière, Emmanuelle Bourdel, Sébastien Quintanel, Bertrand Granado:
VHDL-AMS model of RF-Interconnect System for Global On-Chip Communication. FDL 2010: 155-158 - Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke:
Towards Abstract Analysis Techniques for Range Based System Simulations. FDL 2010: 159-164 - Chenxu Zhao, Tom J. Kazmierski:
Genetic-Based High-Level Synthesis of Sigma-Delta Modulator in SystemC-A. FDL 2010: 165-170
LBSD4: Synthesis for SoC and Beyond
- David J. Greaves, Myoung Jin Nam:
Synthesis of Glue Logic, Transactors, Multiplexors and Serialisors from Protocol Specifications. FDL 2010: 171-177 - Jan Kuper, Christiaan Baaij, Matthijs Kooijman:
Exercises in Architecture Specification Using CLaSH. FDL 2010: 178-183 - Robert Wille, Sebastian Offermann, Rolf Drechsler:
SyReC: A Programming Language for Synthesis of Reversible Circuits. FDL 2010: 184-189
UMES1: Model Driven Approaches for the Development of Embedded Systems
- Matthias Brettschneider, Tobias Häberlein:
Functional Abstractions for UML Activity Diagrams. FDL 2010: 191-196 - Pablo Peñil, Fernando Herrera, Eugenio Villar:
Formal Foundations for MARTE-SystemC Interoperability. FDL 2010: 197-202 - Padma Iyenghar, Clemens Westerkamp, Juergen Wuebbelmann, Elke Pulvermüller:
An Architecture for Deploying Model Based Testing in Embedded Systems. FDL 2010: 203-208
SystemC AMS Extensions
- François Pêcheux, Amer Habib:
Towards High-Level Executable Specifications of Heterogeneous Systems with SystemC-AMS: Application to a Manycore PCR-CE Lab on Chip for DNA Sequencing. FDL 2010: 210-215 - Sumit Adhikari, Christoph Grimm:
Modeling Switched Capacitor Sigma Delta Modulator Nonidealities in SystemC-AMS. FDL 2010: 216-221 - Monica Rafaila, Jérôme Kirscher, Christian Decker, Georg Pelz, Christoph Grimm:
Design of Experiments for Reliable Operation of Electronics in Automotive Applications. FDL 2010: 222-227 - Thomas Arndt, Thomas Uhle, Karsten Einwich, Ingmar Neumann:
Using SystemCAMS for Heterogeneous Systems Modelling at TIER-1 Level. FDL 2010: 228-233 - Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann:
An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL 2010: 234-239
UMES2: Time modelling with MARTE
- Calin Glitia, Julien DeAntoni, Frédéric Mallet:
Logical Time at Work: Capturing Data Dependencies and Platform Constraints. FDL 2010: 241-
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