default search action
17th Asian Test Symposium 2008: Sapporo, Japan
- 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008. IEEE Computer Society 2008, ISBN 978-0-7695-3396-4
Papers
- Anshuman Chandra, Rohit Kapur:
Not All Xs are Bad for Scan Compression. 7-12 - Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams:
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. 13-18 - Jaan Raik
, Hideo Fujiwara, Raimund Ubar
Untestable Fault Identification in Sequential Circuits Using Model-Checking. 21-26 - Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. 27-34 - Alberto Bosio, Giorgio Di Natale:
LIFTING: A Flexible Open-Source Fault Simulator. 35-40 - Hsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, Kwang-Ting (Tim) Cheng
Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs. 43-48 - Abhilash Goyal, Madhavan Swaminathan:
Low-Cost One-Port Approach for Testing Integrated RF Substrates. 49-54 - Deuk Lee, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee:
Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems. 55-60 - Katherine Shu-Min Li, Jr-Yang Huang:
Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization. 63-68 - Nitin Yogi, Vishwani D. Agrawal:
Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns. 69-74 - Jishun Kuang, Ouyang Xiong, Zhiqiang You:
A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself. 75-80 - Sunghoon Chun, YongJoon Kim, Taejin Kim, Myung-Hoon Yang, Sungho Kang:
XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults. 83-88 - Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. 89-96 - Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. 97-102 - Koji Asami, Hidetaka Suzuki, Hiroyuki Miyajima, Tetsuya Taura, Haruo Kobayashi:
Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity. 105-110 - Jin-Fu Lin, Te-Chieh Kung, Soon-Jyh Chang:
A Reduced Code Linearity Test Method for Pipelined A/D Converters. 111-116 - Jui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang:
Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry. 117-122 - Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. 125-130 - Ming-Ting Hsieh, Shun-Yen Lu, Jing-Jia Liou, Augusli Kifli:
High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths. 131-136 - Sean H. Wu, Sreejit Chakravarty, Alexander Tetelbaum, Li-C. Wang
Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay. 142-144 - Salem Abdennadher:
Effects of Advances in Analog, Mixed Signal and IO Circuits on Test Strategies. 145 - Leslie Khoo:
Electrical Overstress Prevention & Test Best Practices. 146 - Akinori Maeda:
Low Distortion Sine Waveform Generation by an AWG. 147 - Taejin Kim, Sunghoon Chun, YongJoon Kim, Myung-Hoon Yang, Sungho Kang:
An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme. 151-156 - Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman:
Optimizing Test Data Volume Using Hybrid Compression. 157-162 - Seongmoon Wang, Wenlong Wei:
Cost Efficient Methods to Improve Performance of Broadcast Scan. 163-169 - Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma:
Hyperactive Faults Dictionary to Increase Diagnosis Throughput. 173-178 - Wu-Tung Cheng, Brady Benware, Ruifeng Guo
Enhancing Transition Fault Model for Delay Defect Diagnosis. 179-184 - Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li:
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. 190-192 - Hagen Goller:
The HiZ Problem of Power Management IC Testing. 193 - Takahiro J. Yamaguchi, Masahiro Ishida:
Total Jitter Measurement for Testing HSIO Integrated SoCs. 194 - Fidel Muradali, Suzanne Huh, Madhavan Swaminathan:
Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning. 195 - Junichi Hirase:
Defect Detection Rate through IDDQ for Production Testing. 199-205 - Urban Ingelsson, Bashir M. Al-Hashimi, Peter Harrod:
Variation Aware Analysis of Bridging Fault Testing. 206-211 - Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. 217-220 - Anis Uzzaman:
How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This? 221 - Görschwin Fey
Targeting Leakage Constraints during ATPG. 225-230 - Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Power Management for Wafer-Level Test During Burn-In. 231-236 - Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor:
Test Generation for State Retention Logic. 237-242 - Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. 245-250 - Nan-Cheng Lai, Sying-Jyan Wang:
On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests. 251-256 - Nobutaka Kito, Naofumi Takagi
Level-Testability of Multi-operand Adders. 260-262 - Fei Zhuang, Junbo Jia, Xiangfeng Li:
System Level LBIST Implementation. 263 - Jun Matsushima, Yoichi Maeda, Masahiro Takakura:
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. 264 - Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami:
Practical Challenges in Logic BIST Implementation. 265 - Keanhong Boey, Kok Sing Yap, Wai Mun Ng:
USB2.0 Logic Built In Self Test Methodology. 266 - Tomonori Sasaki, Yoshiyuki Nakamura, Toshiharu Asaka:
Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes. 267 - Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock. 268 - Katayama Takayuki, Kou Ebihara, Goro Imaizumi:
Leading Edge Technology and Test Noise. 269 - Ricky Smith, Jiang Shi:
DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits. 270 - Khairul Khusyari, Wei Tee Ng, Neal Jaarsma, Robert Abraham, Peng Weng Ng, Boon Hui Ang, Chin Hu Ong:
Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method. 271 - Nobuyuki Hirai:
Detectability of the Two-Dimensional Detector for Time Resolved Emission Measurement. 272 - Shawn Molavi, Andy Evans, Ray Clancy:
Protocol Aware Test Methodologies Using Today. 273 - Anders Larsson, Xin Zhang, Erik Larsson
Core-Level Compression Technique Selection and SOC Test Architecture Design. 277-282 - Zhiyuan He, Zebo Peng, Petru Eles:
Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip. 283-288 - Hyunbean Yi, Sungju Park, Sandip Kundu:
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC. 289-294 - Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman
Accelerated Functional Testing of Digital Microfluidic Biochips. 295-300 - Xiao Liu, Qiang Xu
On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation. 303-308 - Kun-Han Tsai, Ruifeng Guo
A Robust Automated Scan Pattern Mismatch Debugger. 309-314 - Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs. 315-320 - Haihua Shen, Wenli Wei, Yunji Chen
Coverage Directed Test Generation: Godson Experience. 321-326 - Xijiang Lin, Janusz Rajski:
Test Power Reduction by Blocking Scan Cell Outputs. 329-336 - Chao-Wen Tzeng, Shi-Yu Huang:
Two-Gear Low-Power Scan Test. 337-342 - Gui Dai, Zhiqiang You, Jishun Kuang, Jiedi Huang:
DCScan: A Power-Aware Scan Testing Architecture. 348-455 - Yu-Jen Huang, Jin-Fu Li:
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips. 357-362 - Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen:
A Software-Based Test Methodology for Direct-Mapped Data Cache. 363-368 - Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, Kwang-Ting (Tim) Cheng
Time-Multiplexed Online Checking: A Feasibility Study. 371-376 - Stefano Di Carlo, Giorgio Di Natale, Riccardo Mariani:
On-Line Instruction-Checking in Pipelined Microprocessors. 377-382 - Ming Li, Shiyi Xu, Enjun Xia, Fayu Wang:
Design of FSM with Concurrent Error Detection Based on Viterbi Decoding. 383-388 - Yi-Tsung Lin, Meng-Fan Wu, Jiun-Lang Huang:
PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment. 391-396 - Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. 397-402 - Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill:
Power Analysis and Reduction Techniques for Transition Fault Testing. 403-408 - Stefano Di Carlo, Alessandro Savino
Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells. 411-416 - Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu
Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault. 417-422 - Hubert Werkmann, Dong-Myong Kim, Shinji Fujita:
GDDR5 Training. 423-428 - Doochul Shin, Sandeep K. Gupta:
A Re-design Technique for Datapath Modules in Error Tolerant Applications. 431-437 - Ying Zhang, Huawei Li
Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. 438-443 - Koichi Bando, Kenji Tanaka:
Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of Dependability. 444-450
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-18 18:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: