Verilator open-source SystemVerilog simulator and lint system

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

SystemC Reference Implementation

RISC-V SystemC-TLM simulator

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

Network on Chip Simulator

SystemC/TLM-2.0 Co-simulation framework

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A modeling library with virtual components for SystemC and TLM simulators

QEMU libsystemctlm-soc co-simulation demos.

Basic RISC-V Test SoC

A SystemC productivity library: https://minres.github.io/SystemC-Components/

A Framework for Design and Verification of Image Processing Applications using UVM

Brief SystemC getting started tutorial

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Constrained random stimuli generation for C++ and SystemC

Virtio implementation in SystemVerilog

An example of using Ramulator as memory model in a cycle-accurate SystemC Design