document layout analysis results

Digital VLSI Soc-Physical Design (Picorv32)

Designing of a switch box for FPGA circuits in Cadence Virtuoso software. Circuit analysis and implementation of the physical layout.

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.