RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

Human Resource Machine - CPU Design #HRM

Norsk Data ND-120 CPU Design Documents. Modern Logisim and HDL implementation

4 bit CPU (logisim, verilog)

This repo contains all the Verilog HDL files that I made during the course.

This is an implementation of a simple CPU in Logisim and Verilog.

A completely functional encryption decryption model with specially generated Asymmetric key verification

Automatic Door Controller built as a part of Mini Project for course CO202 - Design of Digital Systems

BUAA Computer Organization Project4 CPU monocycle

北航计算机学院 2022 年计算机组成原理 CO 课程设计

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

🖱️ "Digital Electronics Repo: A collection of digital circuits and simulations developed during the Digital Design Lab, organized for effective learning."

Switching Theory's Lab(CS226) containing Logisim and Verilog assignments

计组小白的上机

simple mips architecture

CO-202 Mini Project. A modified implementation of the Enigma machine used in World War II using digital electronics with computer aided design

Arithmetic Unit, Arithmetic Logic Unit and Data Transferring using Tri-state Buffer register have been implemented using flip-flops and gates in Logisim.

Designing a simple processor using Logisim, implementing it using the Verilog programming language, and writing an assembler