VHDL code examples for a digital design course

The design and implementation of simple computer by quartus.

This repository contains the codes for various type of circuits simulated in VHDL in Xilinx ISE Design.

Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.

北邮数字逻辑课程设计之电子钟

VHDL Code for Labs done in a 2nd year Digital Systems course at Queen's University.

VHDL and Verilog Codes for Digital Lab.

北邮数字逻辑课程设计之药片管理系统

VHDL project for a single-bit memory cell. Demonstrates digital logic design.

Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano

This is my final project for digital logic in the third semester of university.

This was the project assignment for the Digital Logic Design course.

Final test of Digital Logic course (Polytechnic of Milan, 2022/23 A.Y.)

Design of a digital clock in VHDL. Course Assignment of COL215: Digital Logic and Systems Design taught in First Sem, 2020-21 at IIT Delhi

Digitial Logic and System Design course at IIT Delhi | Assignments

Assignments for ECSE 222 - Digital Logic (F2022)

ECSE 323 Labs: FPGA programming and digital systems design experiments

Digital Logic course's final test (Polytechnic of Milan, 2022/23 A.Y.)