Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..

HLS-based Xilinx ICAP3 Controller (tested with VCU108)

EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

CMake for Xilinx Vivado/Vitis

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).

Comprehensive open-source curriculum for mastering heterogeneous computing architectures and optimization.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

Custom IP for the Mini-EUSO PDM-DP Zynq system