Klessydra is a family of RISC-V processing cores and accelerators developed at the Digital Systems Lab at Sapienza University of Rome. Klessydra since its begnning has evolved a great deal, and continues to evolve at an accelerated pace.
Some of our works:
- The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes
- Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
- Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation
- Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors
- Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
- Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes
Cite and Share if you use the Klessydra Architecture IPs for an academic publication.