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Implementation of the Advanced Encryption Standard in Chisel

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Implementation of the Advanced Encryption Standard (AES) in Chisel

Motivation

  • Implement an open-source, transparent, secure encryption module in Chisel
  • Equip developers with ready-to-use, efficient, parameterizable, encryption macros for RISC-V systems
  • Compare performance and resource utilization of generated HDL with pure Verilog and Vivado HLS
  • Compare code size with Verilog, Python, C++ and Vivado HLS as a index of development productivity

Features

  • (more to come)
  • Compact AES Cipher and Inverse Cipher Chisel implementation
  • Basic side-channel attack defense based on LFSR noise
  • IDE (IntelliJ) compatible

Instructions

  • Run ./aes_tests.sh > logfile.txt to run all tests and store console output into logfile
  • Generated Verilog will be in directory /test_run_dir
  • Either gtkwave or dinotrace (or other wave viewer) can be used to display .vcd files

References

Citation

This work resulted in the folowwing publications:

@article{guo2022agile,
  title={Agile-AES: Implementation of configurable AES primitive with agile design approach},
  author={Guo, Xinfei and El-Hadedy, Mohamed and Mosanu, Sergiu and Wei, Xiangdong and Skadron, Kevin and Stan, Mircea R},
  journal={Integration},
  year={2022},
  publisher={Elsevier}
}
@inproceedings{mosanu2019flexi,
  title={Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints},
  author={Mosanu, Sergiu and Guo, Xinfei and El-Hadedy, Mohamed and Anghel, Lorena and Stan, Mircea},
  booktitle={2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
  pages={338--338},
  year={2019},
  organization={IEEE}
}