PyCAD: Python Package for Digital Circuit and Computer Aided Design (CAD) Research

This package is written to cover different methods used for circuit netlists (graphs). The package reads the standard format circuit netlists and can perfom different computer aided design operations, including:

• Basic operations:
  • Gate level logical simulation (binary and ternary)
• Design for test (DFT):
  • Fault analysis, e.g. dominancy and equivalency relations
  • Testability measures (SCOAP)
  • Fault simulation (PFS, DFS, PPSF)
  • Systematic fault dropping (CPT)
  • Automatic test pattern generation (ATPG), different versions of D-Algorithm and PODEM
  • Test pattern generation
  • Logic built-in self test (LBIST):
  • Random test pattern analysis and testability measures (STAFAN)
• Translation between different formats of circuits (.bench, .verilog, .ckt)
• Statistical static timing analysis (SSTA)

The package is capable of producing test-related datasets later used in down stream machine learning applications.

Developers and Affiliation:

PyCAD development was first started by a group of graduate students at the University of Southern California (USC) computer engineering as a joint research project with The System Power Optimization and Regulation Technology (SPORT) Lab.

Main developers:
M. Saeed Abrishami
Ghazal Rafiei

Graduate students who worked with this platform during their EE658 course
Luke Grantham
Yang Shen

Advisors:
Prof. Massoud Pedram
Prof. Shahin Nazarian

Setup Environment

Python3

Circuit Input Format

The initial implementation was aimed for test of digital circuits. on a modified version of .CKT, referred as CKT658 [reference]. A translator is availabel to convert standard .bench format to CKT658 and implemented inside the platform. translator.py

Run code

At the command line, type below commands:

cd src/

python3 main.py

To run ATPG, type command:

python3 atpg_v0.py c17

c17 can be replaced with other circuits' name such as c432, c880, c1355...

source codes:

classdef.py is the source code class node, it specifies attributes and methods for a node.

translator.py is the source code to translate bench file to ckt

cread.py is the source code to read input ckt file and instatiate class node

lev.py is the source code for levelization of nodes

logicsim.py is the source code for logic simulation

flr.py is the source code for fault list reduction. The function is tested with c17 circuit

dfs.py is the source code for deductive fault simulation

pfs.py is the source code for parallel fault simulation. The faults dectected by given input sequence is generated to an output file called pfsoutput.txt. The function is tested with c17 circuit

faultdict_gen.py is the source code for generating fault dictionary. Generate a full_fault_list.txt for pfs.py to get the fault dictioanry. Output result in fault_dict.txt. PS: Changed pfs parameter format to achieve this function. Return a dictionary for Equvilance checking. The function is tested with c17 circuit -- Problem: different size of bianry????

mini_faultlist_gen.py is the source code for generating minimum size of fault list. Uitilize faut list from flr and fault dictionary to get minimum fault list. Output result of mini fault list is in mini_faultlist.txt.Output result of reduced fault list is in reduce_faultlist_file PS: The function is tested with c17 circuit

pattern_information.py use greedy to find the reduced test pattern, always find the test pattern that can detect the most remaining fault, the program will end when all the faults are detected, time complexity O(V + E)

equv_domain.py is the source code for generating all the equivalence and domainance by going through the fault dictionary. PS: The function is tested with c17 circuit

checker.py is the script to check the fault coverage of D algrithm and Podem. For smaller circuits: If D / Podem algorithm succceeded, it checks if the test patterns D / Podem algorithm generated are valid (found in fault dictionary). If D / Podem algorithm failed, it checks if the fault is really undetectable by checking the fault dictionary. For bigger circuits, since creating a fault dictionary takes too long time, it simply performs checks on the detected faults and its corresponding patterns returned by D / Podem, using parallel fault simulation to check if those patterns are valid for its fault therefore proves the correctness of P / Podem.

d_alg.py is the source code for d algorithm in recursive manner.

main.py is the source code for main function for testing. c17.ckt658 is used as testing input

MT.cpp is the source code for multithreading fault dictionary generation. Each thread calls parallel_processing.py and generate a partial fault dictionary. This could speed up the fault dictionary generation significantly.

To run this code, type command:

g++ MT.cpp -o MT -pthread && ./MT [CIRCUIT_NAME]

atpg_vo.py is the source code for implementtation of ATPG. Given circuit, atpg will return fault coverage, timing and respondning the number of input pattern. The detail explanations have been written in atpg_v0_report.pdf in documents repo

Repository Structures

source codes are included in src/ folder

input & output files are included in tests/ folder

circuit file. like .ckt and .bench, and description files of the circuits are included in circuits/ folder

fault dictionaries are included in fault_dic/ folder

documents includes some rerferences and reports