CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

FPGA exercise for beginners

My VS Code settings and extensions

| SCHOOL_42_UPDATE 2020 | This repository contains ALL PROJECTS, TASKS AND SUBJECTS OF THE MAIN PROGRAM OF LEARNING AT SCHOOL 42 ( Program | Course | Programing | Coding | School 42 | Ecole 42 | Sc…

Mad intensive course from Moscow campus of intra42

VeeR EH1 core

FuseSoC-based SoC for VeeR EH1 and EL2

Скрипт, позволяющий спарсить расписание с сайта МИЭТ в ics-файл

GoodbyeDPI — Deep Packet Inspection circumvention utility (for Windows)

Web-extension for bypassing censorship in Russia

Amnezia VPN Client (Desktop+Mobile)

网络摄像头漏洞扫描工具 | Webcam vulnerability scanning tool

Learn systemC with examples

SystemVerilog language-oriented exercises

Package manager and build abstraction tool for FPGA/ASIC development

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Задание RTL и RTL Pro треков хакатона SoC Design Challenge 2024

A Python implementation of SNR and SINAD metrics, using Numpy and Numba

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Репозиторий факультатива по функциональной верификации НИУ МИЭТ

Converts an image (PNG) to .mif for Altera memory image files.

SystemVerilog language-oriented exercises

🌊 Digital timing diagram rendering engine

VSCode extension for interacting with Vivado installed on a vagrant machine

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.