Intel 8237

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

• Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero.^[5]
• Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.^[5]
• Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.^[5]
• Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.^[5]

Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.^[5]

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.^[5]

The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so.

In single mode only one byte is transferred per request. For every transfer, the counting register is decremented and address is incremented or decremented depending on programming. When the counting register reaches zero, the terminal count TC signal is sent to the card.^[6][7]

The DMA request DREQ must be raised by the card and held active until it is acknowledged by the DMA acknowledge DACK.^[6]

The transfer is activated by the DREQ which can be deactivated once acknowledged by DACK. The transfer continues until end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.^[6]

The transfer is activated by DREQ and acknowledged by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or external EOP may activate auto-initialization if this is programmed.^[6]

The internal registers used in the 8237 for data transfer are as follows:

• Base address register: To store the initial address from where data transfer will take place
• Base word count register: To store the number of transfers to be performed
• Current address register: To store the current address from where data is being transferred
• Current word count register: To store the number of transfers remaining to be performed
• Temporary address register: To hold address of data during memory-to-memory transfer
• Temporary word count register: To hold number of transfers to be performed in memory-to-memory transfer
• Mode register: 8-bit register which stores the channel to be used, the operating mode, i.e. the transfer mode, and other transfer parameters
• Command register: 8-bit register which initializes the channel to be used for data transfer
• Request register: 8-bit register used to indicate which channel is requesting for data transfer
• Mask register: 8-bit register used to mask a particular channel from requesting for DMA service
• Status register: 8-bit register used to indicate which channel is currently under DMA service and some other parameters

As a member of the Intel MCS-85 device family, the 8237 is an 8-bit device with 16-bit addressing. However, it is compatible with the 8086/88 microprocessors. The IBM PC and PC XT models (machine types 5150 and 5160) have an 8088 CPU and an 8-bit system bus architecture; the latter interfaces directly to the 8237, but the 8088 has a 20-bit address bus, so four additional 4-bit address latches (all actually part of a single 74LS670 device), one for each DMA channel, are added alongside the 8237 to augment the address counters. However, because these external latches are separate from the 8237 address counters, they are never automatically incremented or decremented during DMA operations, making it impossible to perform a DMA operation across a 64 KiB address boundary. Attempts to cross a 64 KiB boundary in a DMA transfer will wrap around within one 64 KiB block of memory. (For example, if a DMA channel and the associated address latch were programmed to transfer 256 bytes to ascending addresses starting at address 0x3FF8C, instead of transferring to addresses 0x3FF8C through 0x4008B, data would be transferred to addresses 0x3FF8C through 0x3FFFF and then to 0x30000 through 0x3008B.)

The IBM PC AT (machine type 5170) and 100% compatibles use an 80286 CPU and a 16-bit system bus architecture. In addition to the 8237 from the PC and XT models, a second, cascaded 8237 is added, for 16-bit DMA transfers. This is possible, despite the 8237 being an 8-bit device, because the 8237 performs transfers between an I/O port and memory as "fly-by" transfers in which the data is placed onto the bus by the source memory or I/O port and directly read at the same time by the destination I/O port or memory, without being handled by the 8237. For this mode of transfer, the width of the data bus is essentially immaterial to the 8237 (as long as it is connected to a data bus at least 8 bits wide, for programming the 8237 registers). The second 8237 in an AT-class PC provides three 16-bit DMA channels (its channels 1 through 3, named channels 5 through 7 in the PC AT); its channel 0 (named channel 4 in the PC AT) is used in cascade mode to connect the 8237 for 8-bit DMA as the "slave" in the cascade arrangement; the 8237 providing the 16-bit channels is the "master". So that it can address 16-bit words, it is connected to the address bus in such a way that it counts even addresses (0, 2, 4, ...) instead of single addresses. Like the first 8237, it is augmented with four address-extension registers. In an AT-class PC, all eight of the address augmentation registers are 8 bits wide, so that full 24-bit addresses—the size of the 80286 address bus—can be specified. DMA transfers on any channel still cannot cross a 64 KiB boundary. (16-bit DMA is limited to 32,768 16-bit words, even though a DMA channel can count through 65536 addresses; the most-significant bit of the address counter from a 16-bit DMA channel is ignored.) Because the 8237 memory-to-memory DMA mode operates by transferring a byte from the source memory location to an internal temporary 8-bit register in the 8237 and then from the temporary register to the destination memory location, this mode could not be used for 16-bit memory-to-memory DMA, as the temporary register is not large enough. Additionally, memory-to-memory 16-bit DMA would require use of channel 4, conflicting with its use to cascade the 8237 that handles the 8-bit DMA channels. However, on the AT, 8-bit DMA channel 0 is no longer used for DRAM refresh, having been replaced by specialized refresh logic, so it should be possible to perform 8-bit memory-to-memory DMA using channels 0 and 1 without interrupting DRAM refresh.

The design of 8237-based DMA in PC AT compatibles was not updated with the move to the 32-bit CPUs and 32-bit system bus architectures. Consequently, a limitation on these machines is that the 8237 DMA controllers with their companion address "page" extension registers only can address 16 MiB of memory, according to the original design oriented around the 80286 CPU, which itself has this same addressing limitation.^[8] This means that for other memory areas, the data has to be transferred first by DMA from the I/O device to an intermediate buffer in the first 16 MiB of the physical address space, and then moved to the final memory by the CPU; or, in the other direction, it must be transferred from the initial memory to the intermediate buffer by the CPU before being transferred by DMA from that buffer to the I/O device. This technique is called "bounce buffer". In general, it loses any overall speed benefit associated with DMA, but it may be necessary if a peripheral requires to be accessed by DMA due to either demanding timing requirements or hardware interface inflexibility.

In the PS/2 series of computers, IBM did update the DMA hardware to support 32-bit data and addresses in some systems with 80386 CPUs, but they did this by replacing the 8237 with a new DMA controller design. The new design includes an 8237 compatibility mode for downward compatibility with the PC AT.

Although this device may not appear as a discrete component in modern personal computer systems, it does appear within system controller chip sets. For example, the PIIX integrated two 8237 controllers for ISA bus DMA.^[9][10]

• Intel 8284 - Clock generator
• Intel 8288 - Bus controller
• 8250 UART - Asynchronous serial controller (EIA-232)
• Intel 8253 - Programmable Interval Timer (PIT)
• Intel 8255 - Programmable Peripheral Interface (PPI)
• Intel 8259 - Programmable Interrupt Controller (PIC)
• Parallel ATA (P-ATA)
• Industry Standard Architecture (ISA)

• DMA: What it is and How it Works FreeBSD Developers' Handbook. 1997 (internet archive).