Dennard scaling

In semiconductor electronics, Dennard scaling, also known as MOSFET scaling, is a scaling law which states roughly that, as transistors get smaller, their power density stays constant, so that the power use stays in proportion with area; both voltage and current scale (downward) with length.^[1][2] The law, originally formulated for MOSFETs, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named.^[3]

For long MOS transistors (i.e. one side is significantly longer than the other two), with constant electric field inside the MOS, Dennard scaling gives^[4]

$${\displaystyle L\propto S^{-1},W\propto S^{-1},t_{ox}\propto S^{-1},V_{\mathrm {DD} }\propto S^{-1},V_{\mathrm {T} }\propto S^{-1},N_{A}\propto S}$$

where parameters are scaled by a factor of ${\displaystyle S}$.

Property	Symbol	Equation	Scaling exponent (constant field)	Scaling exponent (fixed voltage)
Oxide Capacitance	${\displaystyle C_{ox}}$	${\displaystyle \varepsilon _{ox}/t_{ox}}$	1	1
Device Area	${\displaystyle A}$	${\displaystyle W\cdot L}$	-2	-2
Gate Capacitance	${\displaystyle C_{g}}$	${\displaystyle C_{ox}\cdot W\cdot L}$	-1	-1
Transconductance	${\displaystyle K_{n}}$	${\displaystyle \mu _{n}C_{ox}W/L}$	1	1
Saturation Current	${\displaystyle I_{on}}$	${\displaystyle K_{n}V_{GT}^{2}}$	-1	1
On Resistance	${\displaystyle R_{on}}$	${\displaystyle V_{DD}/I_{on}}$	0	-1
Intrinsic Delay	${\displaystyle t_{pd}}$	${\displaystyle R_{on}C_{g}}$	-1	-2
Power	${\displaystyle P_{av}}$	${\displaystyle f\cdot C\cdot V_{DD}^{2}}$	-2	1
Power Density	${\displaystyle PD}$	${\displaystyle P_{av}/A}$	0	3

Explanation of symbols:

• ${\displaystyle S}$: Scaling factor: a factor by which all the device dimensions and voltages are scaled down.
• ${\displaystyle A}$: Area of the transistor.
• ${\displaystyle W}$: Width of the transistor channel.
• ${\displaystyle L}$: Length of the transistor channel.
• ${\displaystyle C_{ox}}$: Oxide capacitance: the capacitance per unit area of the gate dielectric layer (the oxide layer).
• ${\displaystyle \varepsilon _{ox}}$: Permittivity of the oxide layer: a measure of how well the oxide layer can store electrical energy.
• ${\displaystyle t_{ox}}$: Thickness of the oxide layer.
• ${\displaystyle C_{g}}$: Total capacitance of the gate electrode.
• ${\displaystyle K_{n}}$: Transconductance parameter: a measure of how much the drain current changes in response to a change in the gate voltage.
• ${\displaystyle \mu _{n}}$: Electron mobility in the channel: a measure of how easily electrons can move through the channel.
• ${\displaystyle I_{on}}$: Saturation current: the maximum current that can flow through the transistor when it is turned on.
• ${\displaystyle V_{GT}}$: Gate overdrive voltage: the difference between the gate voltage and the threshold voltage.
• ${\displaystyle R_{on}}$: Resistance of the transistor when it is turned on.
• ${\displaystyle V_{DD}}$: Supply voltage: the voltage that is applied to the transistor.
• ${\displaystyle t_{pd}}$: Intrinsic delay: the time it takes for the transistor to switch from on to off or vice versa.
• ${\displaystyle P_{av}}$: Average power consumption: the average amount of power that the transistor consumes.
• ${\displaystyle f}$: Operating frequency: the frequency at which the transistor is switching.
• ${\displaystyle PD}$: Power density: power consumption per unit area.

In fixed voltage scaling, the supply voltage ${\displaystyle V_{DD}}$ is held constant (at ~5V) instead of scaling like ${\displaystyle V_{\mathrm {DD} }\propto S^{-1}}$. This results in different scaling exponents. The clock frequency grows faster at ${\displaystyle S^{2}}$ instead of ${\displaystyle S^{1}}$, but at the price of rapidly increasing power density ${\displaystyle PD\propto S^{3}}$.

Fixed voltage scaling was the common scaling regime which ended around 2005 at the "power wall", when it was too difficult to keep the chip cool. Furthermore, at constant supply voltage, the field grows like ${\displaystyle S^{1}}$, and the off-current grows exponentially with the field, resulting in high static power consumption since the 90 nm node.

Dennard's model of MOSFET scaling implies that, with every technology generation:

1. Transistor dimensions could be scaled by −30% (0.7×). This has the following effects simultaneously:
   • The area of an individual device reduces by 51%, because area is length times width.
   • The capacitance associated with the device, C, is reduced by 30% (0.7×), because capacitance varies with area over distance.
   • To keep the electric field unchanged, the voltage, V, is reduced by 30% (0.7×), because voltage is field times length.
   • Characteristics such as current and transition time are likewise scaled down by 30%, due to their relationship with capacitance and voltage.
   • Overall circuit delay is assumed to be dominated by transition time, so it too is reduced by 30%.
   • Frequency f can increase by about 40% (1.4×), because frequency varies with one over delay.
2. Power consumption of an individual transistor decreases by 51%, because active power is CV²f.^[5]
3. As a result, power consumption per unit area remains the same for every technology generation. Alternatively, with every generation the number of transistors in a chip can be doubled with no change in power consumption.

Moore's law says that the number of transistors on a microchip doubles approximately every two years. Combined with Dennard scaling, this means that performance per joule grows even faster, doubling about every 18 months (1.5 years). This trend is sometimes referred to as Koomey's law. The rate of doubling was originally suggested by Koomey to be 1.57 years,^[6] but more recent estimates suggest this is slowing.^[7]

The dynamic (switching) power consumption of CMOS circuits is proportional to frequency.^[8] Historically, the transistor power reduction afforded by Dennard scaling allowed manufacturers to drastically raise clock frequencies from one generation to the next without significantly increasing overall circuit power consumption.

Specifically, leakage current and threshold voltage do not scale with size, and so the power density increases with scaling. This eventually led to a power density that is too high. This is the "power wall", which caused Intel to cancel Tejas and Jayhawk in 2004.^[9]

Since around 2005–2007 Dennard scaling appears to have broken down. As of 2016, transistor counts in integrated circuits are still growing, but the resulting improvements in performance are more gradual than the speed-ups resulting from significant frequency increases.^[1][10] The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs.^[1][10] Since 2005, the clock frequency has stagnated at 4 GHz, and the power consumption per CPU at 100 W TDP.

The breakdown of Dennard scaling and resulting inability to increase clock frequencies significantly has caused most CPU manufacturers to focus on multicore processors as an alternative way to improve performance. An increased core count benefits many (though by no means all – see Amdahl's law) workloads, but the increase in active switching elements from having multiple cores still results in increased overall power consumption and thus worsens CPU power dissipation issues.^[11][12] The end result is that only some fraction of an integrated circuit can actually be active at any given point in time without violating power constraints. The remaining (inactive) area is referred to as dark silicon.

• “The Impact of Dennard’s Scaling Theory”, SSCS Magazine, Winter 2007