F16C

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The F16C^[1] (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.

The CVT16 instruction set, announced by AMD on May 1, 2009,^[2] is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set.

CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.

In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications.

There are variants that convert four floating-point values in an XMM register or 8 floating-point values in a YMM register.

The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:

• VCVTPH2PS xmmreg,xmmrm64 – convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register.
• VCVTPH2PS ymmreg,xmmrm128 – convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register.
• VCVTPS2PH xmmrm64,xmmreg,imm8 – convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.
• VCVTPS2PH xmmrm128,ymmreg,imm8 – convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.

The 8-bit immediate argument to VCVTPS2PH selects the rounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set in MXCSR.RC.

Support for these instructions is indicated by bit 29 of ECX after CPUID with EAX=1.

• AMD:
  • Jaguar-based processors
  • Puma-based processors
  • "Heavy Equipment" processors
    • Bulldozer-based processors, Q4 2011^[3]
    • Piledriver-based processors, Q4 2012^[4]
    • Steamroller-based processors, Q1 2014
    • Excavator-based processors, Q2 2015
  • Zen-based processors, Q1 2017, and newer
• Intel:
  • Ivy Bridge processors and newer

• New Bulldozer and Piledriver Instructions [1] Archived 2013-01-07 at the Wayback Machine
• DirectX math F16C and FMA [2]
• AMD64 Architecture Programmer's Manual Volume 1 [3] Archived 2013-12-14 at the Wayback Machine
• AMD64 Architecture Programmer's Manual Volume 2 [4]
• AMD64 Architecture Programmer's Manual Volume 3 [5] Archived 2013-12-14 at the Wayback Machine
• AMD64 Architecture Programmer's Manual Volume 4 [6] Archived 2021-11-14 at the Wayback Machine
• AMD64 Architecture Programmer's Manual Volume 5 [7] Archived 2013-12-14 at the Wayback Machine
• IA32 Architectures Software Developer Manual [8]