Blackfin

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Blackfin

ADI Blackfin Logo
General information
Launched	2008
Discontinued	Present
Marketed by	Analog Devices
Designed by	Analog Devices
Common manufacturer	Analog Devices

Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality performed by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller.^[1] It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.^[2][3]

Blackfin processors use a 32-bit RISC microcontroller programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.

It incorporates aspects of ADI's older SHARC architecture and Intel's XScale architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications.^[4] The BF-7xx series, introduced in 2014, comprise the Blackfin+ architecture, which expands on the Blackfin architecture with some new processor features and instructions.

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What is regarded as the Blackfin "core" is contextually dependent. For some applications, the DSP features are central. Blackfin has two 16-bit hardware MACs, two 40-bit ALUs and accumulators, a 40-bit barrel shifter, and four 8-bit video ALUs; Blackfin+ processors add a 32-bit MAC and 72-bit accumulator. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications use the RISC features, which include memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present. The standard Blackfin assembly language is written using an algebraic syntax: instead of prefix commands used in many other assembly languages.

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space, so that from a programming point of view, the Blackfin has a Von Neumann architecture.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and SRAM. Some Blackfin processors also include mass-storage interfaces such as ATAPI and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which is designed for higher throughput for applications that can use it, such as real-time standard-definition (D1) video encoding and decoding.

The architecture of Blackfin contains the usual CPU, memory, and I/O that is found on microprocessors or microcontrollers. These features enable operating systems.

All Blackfin processors contain a Memory Protection Unit (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support operating systems, RTOSs and kernels like ThreadX, μC/OS-II, or NOMMU Linux. Although the MPU is referred to as a Memory Management Unit (MMU) in the Blackfin documentation, the Blackfin MPU does not provide address translation like a traditional MMU, so it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX.

Blackfin supports three run-time modes: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an exception will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space.

Blackfin uses a variable-length RISC-like instruction set consisting of 16-, 32- and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32- and 64-bit opcodes. This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures.

The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and image compression and decompression algorithms.

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Blackfin processors contain an array of connectivity peripherals, depending on the specific processor:

• ATAPI
• CAN: A wide-area, low-speed serial bus used in some automotive and industrial electronics
• DMA with support for memory-to-memory DMA and peripheral DMA
• EMAC (Ethernet Media Access Controller) with MII and RMII
• External memory: the EBIU (External Bus Interface Unit) can include a controller for SDRAM, Mobile SDRAM, DDR1, DDR2, or LPDDR, and an asynchronous memory controller for SRAM, ROM, flash EPROM, and memory-mapped I/O devices
• GPIO including level-triggered and edge-triggered interrupts
• I²C, also known as TWI (Two-Wire Interface): a lower speed, shared serial bus
• MXVR: a MOST Network Interface Controller
• NAND flash
• PPI: A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 75 MHz and can be configured from 8 to 16-bits wide.
• PWM and timers/counters
• Real-time clock
• SD/SDIO
• SPI: a fast serial bus used in some high-speed embedded electronics applications
• SPORT: A synchronous, high speed serial port that can support TDM, I²S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
• UART: allows for bi-directional communication with RS-232 devices (PCs, modems, PC peripherals, etc.), MIDI devices, IRDA devices
• USB 2.0 OTG (On-The-Go)
• Watchdog timer

All of the peripheral control registers are memory-mapped in the normal address space.

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ADI provides its own software development toolchains. The original VisualDSP++ IDE is still supported (its last release was 5.1.2 in October 2014; 10 years ago (2014-10)), but is approaching end of life and has not had support added for the new BF6xx and BF7xx processors. The newer toolchain is CrossCore Embedded Studio, which uses supports all Blackfin and Blackfin+ processors using upgraded versions of the same compiler and tools internally, but with a UI based on Eclipse CDT. No free version of either tool is available; a single-user license for VisualDSP++ costs $3500 USD, and CrossCore Embedded Studio $995 USD.

Other options include Green Hills Software's MULTI IDE and the GNU GCC Toolchain for the Blackfin processor family. However, like VisualDSP++, these have not been updated to support the newer BF6xx and BF7xx processors. Moreover, neither support all BF5xx processors. Green Hills MULTI lacks support for BF50x, BF51x, some BF52x, BF547, and BF59x. GCC lacks support for BF50x, BF566, and BF59x, and has incomplete support for BF561.

Blackfin is also supported by National Instruments' LabVIEW Embedded Module, which requires VisualDSP++.

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Several commercial and open-source operating systems support running on Blackfin.

Blackfin was previously supported by μClinux and later by Linux with the NOMMU feature, but as it was not ever widely used and no longer had a maintainer,^[8][9] support was removed from Linux on April 1, 2018; 4.16 was the last release to include Blackfin support.^[10][11][12]

• SHARC
• TigerSHARC

• Blackfin processor website
• Blackfin Processor Programming Reference
• blackfin.uclinux.org Open source tools and Linux kernel for Blackfin
• T2 SDE A build-system supporting the cross compilation to Blackfin