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Ik Joon Chang
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2020 – today
- 2024
- [j29]Donghyeon Yi
, Seoyoung Lee, Injun Choi
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2067-2078 (2024) - [c31]Nguyen-Dong Ho, Gyujun Jeong, Cheol-Min Kang, Seungkyu Choi, Ik-Joon Chang:
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy. DAC 2024: 52:1-52:6 - [c30]Edward Jongyoon Choi, Vincent Lukito, Injun Choi, Seoyoung Lee, Ik-Joon Chang, Sohmyung Ha, Minkyu Je:
A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j28]Nguyen-Dong Ho
O-2A: Outlier-Aware Compression for 8-bit Post-Training Quantization Model. IEEE Access 11: 95467-95480 (2023) - [j27]Nguyen-Dong Ho
MiCE: An ANN-to-SNN Conversion Technique to Enable High Accuracy and Low Latency. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 1094-1105 (2023) - [j26]Young-Min Kang
Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3619-3623 (2023) - [c29]Thanh-Dat Nguyen, Minh-Son Le, Thi-Nhan Pham, Ik-Joon Chang:
TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks. AICAS 2023: 1-5 - [c28]Edward Jongyoon Choi, Injun Choi, Vincent Lukito, Dong-Hwi Choi, Donghyeon Yi, Ik-Joon Chang, Sohmyung Ha, Minkyu Je:
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation. CICC 2023: 1-2 - [c27]Jung-Jin Park, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim:
Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. ICEIC 2023: 1-4 - 2022
- [j25]Injun Choi
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 536-546 (2022) - [j24]Thi-Nhan Pham
STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 569-579 (2022) - [c26]Edward Jongyoon Choi, Injun Choi, Chanhee Jeon, Gichan Yun
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. CICC 2022: 1-2 - 2021
- [j23]Duy Thanh Nguyen
ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM. IEEE Access 9: 93723-93733 (2021) - [j22]Duy Thanh Nguyen
OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems. Sensors 21(24): 8271 (2021) - [c25]Nguyen-Dong Ho, Ik-Joon Chang:
TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. DAC 2021: 793-798 - [c24]Nhut-Minh Ho
Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks. DATE 2021: 1350-1355 - [c23]Thi-Nhan Pham, Kien Trinh Quang
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. ISCAS 2021: 1-5 - [i2]Minh-Son Le, Thi-Nhan Pham, Thanh-Dat Nguyen, Ik-Joon Chang:
PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory. CoRR abs/2110.09962 (2021) - 2020
- [j21]Duckhoon Ro, Changhong Min, Myounggon Kang
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems. Sensors 20(1): 171 (2020) - [c22]Nguyen-Dong Ho, Minh-Son Le, Ik-Joon Chang:
O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation. DAC 2020: 1-6 - [c21]Boyeal Kim, Sang Hyun Lee, Hyun Kim, Duy Thanh Nguyen, Minh-Son Le, Ik Joon Chang, Dohun Kwon, Jin Hyeok Yoo, Jun Won Choi, Hyuk-Jae Lee:
PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training. DATE 2020: 1199-1204 - [c20]Duy Thanh Nguyen, Changhong Min, Nhut-Minh Ho
DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System. ICCAD 2020: 47:1-47:8 - [c19]Trang Le Dinh Dang
Comparing Variation-tolerance and SEU/TID-Resilience of Three SRAM Cells in 28nm FD-SOI Technology: 6T, Quatro, and we-Quatro. IRPS 2020: 1-5 - [i1]Nguyen-Dong Ho, Ik-Joon Chang:
TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. CoRR abs/2008.04509 (2020)
2010 – 2019
- 2019
- [j20]Moonsoo Kim
Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy. IEEE Trans. Computers 68(10): 1546-1552 (2019) - [c18]Duy Thanh Nguyen, Nhut-Minh Ho
St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs. DAC 2019: 205 - [c17]Duy Thanh Nguyen, Ik-Joon Chang:
Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection. ISOCC 2019: 168-169 - 2018
- [j19]Hyun Kim
Optimal Selection of SRAM Bit-Cell Size for Power Reduction in Video Compression. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 431-443 (2018) - [c16]Trang Le Dinh Dang
A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space Applications. A-SSCC 2018: 133-134 - [c15]Duy Thanh Nguyen, Hyun Kim, Hyuk-Jae Lee, Ik Joon Chang:
An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications. ISCAS 2018: 1-5 - [c14]M. Sultan M. Siddiqui, Ruchi Sharma, Van Loi Le
A Radiation Hardened SRAM with Self-refresh and Compact Error Correction. ISOCC 2018: 235-236 - 2017
- [j18]Ik Joon Chang, Sang Yoon Park, Jun Won Choi
Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation. Circuits Syst. Signal Process. 36(11): 4309-4325 (2017) - 2016
- [j17]Ik Joon Chang, Joon-Sung Yang:
Subthreshold 8T SRAM sizing utilizing short-channel Vt roll-off and inverse narrow-width effect. IEICE Electron. Express 13(8): 20160020 (2016) - [j16]Anh-Tuan Do, Zhao Chuan Lee, Bo Wang
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. IEEE J. Solid State Circuits 51(6): 1487-1498 (2016) - [j15]Minsu Choi, Ik Joon Chang, Jinsang Kim:
Optimal reference view selection algorithm for low complexity disparity estimation. IEEE Trans. Consumer Electron. 62(1): 45-52 (2016) - [c13]My-Kieu Nguyen-Thi, Ik Joon Chang, Jinsang Kim:
Architecture of WLAN channel estimators. APCCAS 2016: 588-590 - [c12]Hyun Kim, Ik Joon Chang, Hyuk-Jae Lee:
An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder. ICCE 2016: 528-529 - 2015
- [j14]Youngkyu Jang, Changnoh Yoon, Ik Joon Chang, Jinsang Kim:
Variation-Aware Flip Flop for DVFS Applications. IEICE Trans. Electron. 98-C(5): 439-445 (2015) - [j13]Youngkyu Jang, Ik Joon Chang, Jinsang Kim:
SET-Tolerant Active Body-Bias Circuits in PD-SOI CMOS Technology. IEICE Trans. Electron. 98-C(7): 729-733 (2015) - [c11]Minsu Choi, Kyung-Rae Kim, Ik Joon Chang, Jinsang Kim:
Low power block matching using pattern based pixel truncation. MWSCAS 2015: 1-4 - 2014
- [j12]HyungJune Lee
CPAC: Energy-Efficient Data Collection through Adaptive Selection of Compression Algorithms for Sensor Networks. Sensors 14(4): 6419-6442 (2014) - [c10]Anh-Tuan Do, Zhao Chuan Lee, Bo Wang
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. A-SSCC 2014: 141-144 - [c9]Trang Le Dinh Dang
a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique. ISLPED 2014: 259-262 - 2013
- [j11]Joon-Sung Yang, Ik Joon Chang:
Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion. IEICE Trans. Electron. 96-C(1): 127-131 (2013) - [j10]Ngoc Dang Phan, Ik Joon Chang, Jong-Wook Lee:
A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 µm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(7): 1810-1822 (2013) - [j9]Minsu Choi, Ik Joon Chang, Jinsang Kim:
High Performance and Hardware Efficient Multiview Video Coding Frame Scheduling Algorithms and Architectures. IEEE Trans. Circuits Syst. Video Technol. 23(8): 1312-1321 (2013) - [c8]Junghyun Ha, Janghyuk Yoon, Ik Joon Chang, Jinsang Kim:
Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad. ISCAS 2013: 2163-2166 - [c7]Wooseok Kim, Joohan Kim, Minsu Choi, Ik Joon Chang, Jinsang Kim:
Low complexity image correction using color and focus matching for stereo video coding. ISCAS 2013: 2912-2915 - 2012
- [j8]Ik Joon Chang, Joon-Sung Yang:
Bit-error rate improvement of TLC NAND Flash using state re-ordering. IEICE Electron. Express 9(23): 1775-1779 (2012) - [j7]Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park, Jongsun Park
Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2275-2284 (2012) - [c6]Minsu Choi, Jinsang Kim, Ik Joon Chang, Won-Kyung Cho:
Low-complexity frame scheduler using shared frame memory for multi-view video coding. ISOCC 2012: 498-502 - [c5]Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. ISSCC 2012: 430-432 - 2011
- [j6]Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy:
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. IEEE Trans. Circuits Syst. Video Technol. 21(2): 101-112 (2011) - [j5]Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy:
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1429-1437 (2011) - 2010
- [j4]Ik Joon Chang, Jongsun Park
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. IET Circuits Devices Syst. 4(6): 469-478 (2010) - [j3]Ik Joon Chang, Sang Phill Park
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. IEEE J. Solid State Circuits 45(2): 401-410 (2010)
2000 – 2009
- 2009
- [j2]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits 44(2): 650-658 (2009) - [c4]Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy:
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. DAC 2009: 670-675 - 2008
- [c3]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. ISSCC 2008: 388-389 - 2006
- [j1]Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy:
PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits 41(1): 170-178 (2006) - [c2]Ik Joon Chang, Jae-Joon Kim, Kaushik Roy:
Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19 - 2005
- [c1]Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy:
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. CICC 2005: 439-442
Coauthor Index
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