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Tetsuya Fujita
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2010 – 2019
- 2013
- [c9]Ryosuke Saga
, Tetsuya Fujita, Kodai Kitami, Kazunori Matsumoto:
Improvement of Factor Model with Text Information Based on Factor Model Construction Process. IIMSS 2013: 222-230 - 2011
- [j9]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki:
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits 46(1): 32-41 (2011) - [c8]Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa:
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. COOL Chips 2011: 1-3 - [c7]Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada:
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. ISSCC 2011: 338-340 - 2010
- [c6]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki:
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC 2010: 326-327
2000 – 2009
- 2009
- [j8]Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi:
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications. IEEE J. Solid State Circuits 44(11): 2957-2965 (2009) - [c5]Masaki Ogino, Tetsuya Fujita, Sawa Fuke, Minoru Asada:
Learning of situation dependent prediction toward acquiring physical causality. EpiRob 2009 - 2008
- [c4]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263 - 2006
- [j7]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006) - [j6]Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki:
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1379-1383 (2006) - 2005
- [c3]Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki:
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC 2005: 527-530 - 2003
- [j5]Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa:
A single-chip 802.11a MAC/PHY with a 32-b RISC processor. IEEE J. Solid State Circuits 38(11): 2001-2009 (2003)
1990 – 1999
- 1998
- [j4]Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama:
Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits 33(3): 454-462 (1998) - [j3]Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama:
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33(11): 1772-1780 (1998) - 1996
- [j2]Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray:
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits 31(6): 819-827 (1996) - [j1]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai:
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE J. Solid State Circuits 31(11): 1770-1779 (1996) - [c2]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai:
Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED 1996: 309-312
1980 – 1989
- 1988
- [c1]Robert H. Halstead Jr., Tetsuya Fujita:
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. ISCA 1988: 443-451
Coauthor Index
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